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1.发明授权公开(公告)号：US06670228B2
公开(公告)日：2003-12-30
申请号：US10339151
申请日：2003-01-09
IPC分类号： H01L218238
CPC分类号： H01L28/40 , H01L21/8249 , H01L27/0635 , Y10S438/951
摘要： A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.
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2.发明授权Bipolar transistor structure with a shallow isolation extension region providing reduced parasitic capacitance 失效具有浅隔离延伸区域的双极晶体管结构，提供降低的寄生电容公开(公告)号：US06864560B2
公开(公告)日：2005-03-08
申请号：US10249299
申请日：2003-03-28
申请人： Marwan H. Khater , Jae-Sung Rieh , Andreas Daniel Stricker , Gregory Gower Freeman , Kathryn Turner Schonenberg
发明人： Marwan H. Khater , Jae-Sung Rieh , Andreas Daniel Stricker , Gregory Gower Freeman , Kathryn Turner Schonenberg
IPC分类号： H01L29/70 , H01L21/331 , H01L29/732 , H01L29/737 , H01L27/082 , H01L27/102 , H01L31/11
CPC分类号： H01L29/66287 , H01L29/0649 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar vertical transistor is formed in a silicon semiconductor substrate which has an upper surface with STI regions formed therein composed of a dielectric material formed in the substrate having inner ends and top surfaces. A doped collector region is formed in the substrate between a pair of the STI regions. A counterdoped intrinsic base region is formed on the upper surface of the substrate between the pair of the STI regions with a margin between the intrinsic base region and the pair of STI regions, the intrinsic base region having edges. A doped emitter region is formed above the intrinsic base region spaced away from the edges. A shallow isolation extension region composed of a dielectric material is next to the edges of the intrinsic base region formed in the margin between the STI regions and the intrinsic base region. An extrinsic base region covers the shallow isolation extension region and extends partially over the intrinsic base region in mechanical and electrical contact therewith, whereby the shallow isolation extension region reduces the base-to-collector parasitic capacitance of the bipolar transistor.
摘要翻译： 双极性垂直晶体管形成在硅半导体衬底中，该硅半导体衬底具有形成有STI区域的上表面，该区域由形成在具有内端和顶表面的衬底中的电介质材料构成。 掺杂的集电极区域形成在一对STI区域之间的衬底中。 在本体基极区域和一对STI区域之间的边缘部分之间形成反向掺杂的本征基极区域，该反向掺杂的本征基极区域位于一对STI区域之间的衬底的上表面上，本征基极区域具有边缘。 掺杂的发射极区域形成在与边缘间隔开的本征基极区域上方。 由介电材料构成的浅隔离延伸区域紧邻在STI区域和本征基极区域之间的边缘中形成的本征基极区域的边缘。 外部基极区域覆盖浅隔离延伸区域并且在与本体基极区域机械和电接触的同时部分延伸，由此浅隔离延伸区域减小双极晶体管的基极到集电极寄生电容。
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3.发明授权Method of fabricating a polysilicon capacitor utilizing fet and bipolar base polysilicon layers 有权使用电子和双极基底多晶硅层制造多晶硅电容器的方法公开(公告)号：US06800921B1
公开(公告)日：2004-10-05
申请号：US09516615
申请日：2000-03-01
IPC分类号： H01L27108
CPC分类号： H01L28/40 , H01L21/8249 , H01L27/0635 , Y10S438/951
摘要： A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.
摘要翻译： 一种在衬底上同时形成多晶硅多晶硅电容器，MOS晶体管和双极晶体管的方法，包括以下步骤：在衬底上沉积和构图第一层多晶硅以形成所述电容器的第一平板电极和电极 并且在衬底上沉积和构图第二层多晶硅以形成所述电容器的第二平板电极和双极晶体管的电极。
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