公开(公告)号：US20080263486A1

公开(公告)日：2008-10-23

申请号：US12122988

申请日：2008-05-19

申请人： Herve Alexanian ,  Chien-Chun Chou ,  Vida Vakilotojar ,  Grigor Yeghiazaryan

发明人： Herve Alexanian ,  Chien-Chun Chou ,  Vida Vakilotojar ,  Grigor Yeghiazaryan

IPC分类号： G06F17/50

CPC分类号： G06F17/504 ,  G01R31/318314

摘要： Various methods and apparatuses are described for generating a model of hardware components making up an interconnect that facilitates communications between Intellectual Property blocks in an integrated circuit coded in a software programming language at a high level of abstraction that is cycle accurate to a corresponding lower level of abstraction description of the hardware components making up the interconnect. The sub-components of the model at the high level of abstraction are tested in a simulation environment in parallel with the same sub-components of a model coded in a hardware description language at the low level of abstraction in order to verify the functional accuracy and cycle timing between the two models. After the sub-components are tested, the sub-components of the model at the high level of abstraction may be aggregated into a single model at the high level of abstraction that is functionally accurate and cycle accurate to the model at the low level of abstraction.

摘要翻译： 描述了用于生成构成互连的硬件组件的模型的各种方法和装置，其有助于在以高抽象级别编码的集成电路中的知识产权块之间的通信，所述集成电路是循环准确地到相应的较低级别 构成互连的硬件组件的抽象描述。 在高抽象级别的模型的子组件在模拟环境中与在低抽象级别的硬件描述语言中编码的模型的相同子组件并行进行测试，以验证功能精度和 两个模型之间的循环时序。 在子组件被测试之后，在高抽象级别的模型的子组件可以在抽象的高水平聚合成单个模型，其功能准确并且在低抽象级别对模型进行周期准确 。

公开(公告)号：US08020124B2

公开(公告)日：2011-09-13

申请号：US12122988

申请日：2008-05-19

申请人： Herve Alexanian ,  Chien-Chun Chou ,  Vida Vakilotojar ,  Grigor Yeghiazaryan

发明人： Herve Alexanian ,  Chien-Chun Chou ,  Vida Vakilotojar ,  Grigor Yeghiazaryan

IPC分类号： G06F17/50

CPC分类号： G06F17/504 ,  G01R31/318314

摘要： Various methods and apparatuses are described for generating a model of hardware components making up an interconnect that facilitates communications between Intellectual Property blocks in an integrated circuit coded in a software programming language at a high level of abstraction that is cycle accurate to a corresponding lower level of abstraction description of the hardware components making up the interconnect. The sub-components of the model at the high level of abstraction are tested in a simulation environment in parallel with the same sub-components of a model coded in a hardware description language at the low level of abstraction in order to verify the functional accuracy and cycle timing between the two models. After the sub-components are tested, the sub-components of the model at the high level of abstraction may be aggregated into a single model at the high level of abstraction that is functionally accurate and cycle accurate to the model at the low level of abstraction.

摘要翻译： 描述了用于生成构成互连的硬件组件的模型的各种方法和装置，其有助于在以高抽象级别编码的集成电路中的知识产权块之间的通信，所述集成电路是循环准确地到相应的较低级别 构成互连的硬件组件的抽象描述。 在高抽象级别的模型的子组件在模拟环境中与在低抽象级别的硬件描述语言中编码的模型的相同子组件并行进行测试，以验证功能精度和 两个模型之间的循环时序。 在子组件被测试之后，在高抽象级别的模型的子组件可以在抽象的高水平聚合成单个模型，其功能准确并且在低抽象级别对模型进行周期准确 。