公开(公告)号：US07376140B1

公开(公告)日：2008-05-20

申请号：US10107014

申请日：2002-03-25

Applicant: Guillermo A. Franco ,  Scott W. Shumate ,  James W. Edwards, III ,  Michael R. Woodard

Inventor： Guillermo A. Franco ,  Scott W. Shumate ,  James W. Edwards, III ,  Michael R. Woodard

IPC: H04L12/28

CPC classification number: H04L12/5601

Abstract: A method for distributing digital subscriber line (xDSL) data traffic includes receiving xDSL traffic at a DSLAM including a plurality of input ports and a plurality of output queues. Each input port includes a plurality of virtual circuits. Each of the plurality of virtual circuits are dynamically assigned to one of the plurality of output queues. The assignment of any particular virtual circuit to one of the plurality of output queues is independent of which of the plurality of input ports the particular virtual circuit is associated with. In accordance with the particular embodiment, the total number of virtual circuits is greater than a total number of output queues.

Abstract translation: 用于分发数字用户线（xDSL）数据业务的方法包括在包括多个输入端口和多个输出队列的DSLAM处接收xDSL业务。 每个输入端口包括多个虚拟电路。 多个虚拟电路中的每一个被动态分配给多个输出队列之一。 将任何特定的虚拟电路分配给多个输出队列之一是独立于特定虚拟电路相关联的多个输入端口中的哪一个。 根据特定实施例，虚拟电路的总数大于输出队列的总数。

公开(公告)号：US06853643B1

公开(公告)日：2005-02-08

申请号：US09745452

申请日：2000-12-21

Applicant: William P. Hann ,  Guillermo A. Franco ,  Craig D. Botkin ,  James W. Edwards, III

Inventor： William P. Hann ,  Guillermo A. Franco ,  Craig D. Botkin ,  James W. Edwards, III

IPC: H04L12/56 ,  H04M11/06 ,  H04L12/54

CPC classification number: H04M11/062 ,  H04L49/103 ,  H04L49/90 ,  H04L49/901 ,  H04L49/9047

Abstract: An interleaved read/write operation in a data switch determines a read memory of at least two memories that has been accessed during a most recent read operation. A memory controller determines a write memory different from the read memory and accesses a cell buffer list associated with the write memory to determine a buffer to store the cell. The switch writes the cell to the buffer to interleave read/write operations between the read memory and the write memory.

Abstract translation: 数据交换中的交错读/写操作确定在最近的读取操作期间已被访问的至少两个存储器的读存储器。 存储器控制器确定与读取存储器不同的写入存储器并访问与写入存储器相关联的单元缓冲器列表以确定存储单元的缓冲器。 交换机将单元写入缓冲区以在读取存储器和写入存储器之间交错读/写操作。