公开(公告)号：US20130249094A1

公开(公告)日：2013-09-26

申请号：US13990779

申请日：2011-11-28

申请人： Hansong Cheng ,  Guo Qin Xu

发明人： Hansong Cheng ,  Guo Qin Xu

IPC分类号： H01L31/18 ,  H01L51/00

CPC分类号： H01L31/1884 ,  H01B1/08 ,  H01L31/022475 ,  H01L51/0021 ,  H01L51/442 ,  H01L51/5206 ,  Y02E10/50

摘要： The present invention discloses a method of preparing a transparent conducting oxide (TCO) film comprising the steps of: applying surface modified TCO nanoparticles onto a surface of a substrate; and cross-linking the surface modified TCO nanoparticles. The present invention also provides a transparent conducting oxide film prepared according to the method.

摘要翻译： 本发明公开了一种制备透明导电氧化物（TCO）膜的方法，包括以下步骤：将表面改性的TCO纳米颗粒施加到基材的表面上; 并交联表面改性的TCO纳米颗粒。 本发明还提供了根据该方法制备的透明导电氧化物膜。

公开(公告)号：US06251781B1

公开(公告)日：2001-06-26

申请号：US09374312

申请日：1999-08-16

申请人： Mei Sheng Zhou ,  Guo-Qin Xu ,  Lap Chan

发明人： Mei Sheng Zhou ,  Guo-Qin Xu ,  Lap Chan

IPC分类号： H01L2144

CPC分类号： H01L21/76874 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76879 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating single and dual damascene copper interconnects is achieved. A semiconductor substrate layer is provided. Conductive traces are provided in an isolating dielectric layer. An intermetal dielectric layer is deposited overlying the conductive traces and the isolating dielectric layer. The intermetal dielectric layer is patterned to form trenches to expose the top surfaces of the underlying conductive traces. A barrier layer is deposited overlying the intermetal dielectric layer, the exposed conductive traces, and within the trenches. A platinum ionic seed solution is coated inside the trenches and overlying the barrier layer. A platinum seed layer is deposited from the ionic seed solution by exposing the platinum ionic seed solution to ultraviolet light. A copper layer is deposited by electroless plating to form copper interconnects, where the copper layer is only deposited overlying the platinum seed layer in the trenches, and where the deposition stops before the copper layer fills the trenches. The exposed barrier layer is polished down to the top surface of the intermetal dielectric layer. An encapsulation layer is deposited overlying the copper interconnects and the intermetal dielectric layer to complete the fabrication of the integrated circuit device.

摘要翻译： 实现了制造单和双镶嵌铜互连的方法。 提供半导体衬底层。 导电迹线设置在隔离电介质层中。 沉积覆盖导电迹线和隔离电介质层的金属间电介质层。 图案化金属间电介质层以形成沟槽以暴露下面的导电迹线的顶表面。 覆盖在金属间电介质层，暴露的导电迹线和沟槽内的阻挡层被沉积。 将铂离子种子溶液涂覆在沟槽内并覆盖阻挡层。 通过将铂离子种子溶液暴露于紫外光，从离子种子溶液沉积铂种子层。 通过无电镀沉积铜层以形成铜互连，其中铜层仅沉积在沟槽中的铂种子层上方，并且在铜层填充沟槽之前沉积停止。 暴露的阻挡层被抛光到金属间电介质层的顶表面。 沉积覆盖在铜互连和金属间电介质层上的封装层，以完成集成电路器件的制造。