公开(公告)号：US06559697B2

公开(公告)日：2003-05-06

申请号：US10097430

申请日：2002-03-15

申请人： Haruhide Kikuchi

发明人： Haruhide Kikuchi

IPC分类号： H03L706

CPC分类号： H03L7/089 ,  H03L7/0995 ,  H03L7/183 ,  H03L7/199

摘要： A multiplied clock generating circuit for generating and outputting an output clock signal that has a higher frequency than an input clock by a factor M is described. The multiplied clock generating circuit comprising: a frequency divider circuit which is configured to generate a feedback clock signal by dividing the output clock signal by a factor M; a phase comparator circuit which is configured to receive the input clock signal and the feedback clock signal as generated by the frequency divider circuit, to compare the phase of the input clock signal with the phase of the feedback clock signal and to output a phase displacement signal indicative of the phase relationship between the input clock signal and the feedback clock signal; a comparator which is configured to receive the phase displacement signal, to count the output clock signal within each cycle of the feedback clock signal while the phase displacement signal is indicative that there is a phase displacement between the feedback clock signal and the input clock signal, to compare the numbers as counted in successive cycles of the feedback clock signal, and to output a delay time adjustment signal on the basis of the result of the comparison; and an oscillator circuit which is capable of controlling the output clock signal in the clock period thereof by an increment(s) of a predetermined delay time on the basis of the delay time adjustment signal and outputting the output clock signal as controlled.

公开(公告)号：US06202078B1

公开(公告)日：2001-03-13

申请号：US09177558

申请日：1998-10-23

申请人： Haruhide Kikuchi ,  Masayuki Koizumi

发明人： Haruhide Kikuchi ,  Masayuki Koizumi

IPC分类号： G06F752

CPC分类号： G06F7/5443 ,  G06F7/5338

摘要： A booth decoder decodes A or −A according to a booth algorithm, depending upon whether A×B or −A×B should be multiplied. A partial multiplier/partial adder circuit 30 generates partial products of A×B or −A×B following to a result of the decoding, and sequentially adds these partial products. Data C, or data made by inverting bits of C, is input to the partial multiplier/partial adder circuit 30, depending upon whether C should be added or −C should be added to the result of multiplication. Also the data C or data made by inverting bits of C are sequentially added by the partial multiplier/partial adder circuit 30. A final adder circuit 50 executes final addition of these partial products, and adds 1 when −C should be added. Thus, Z=±(A×B)±C (the order of signs being variable) can be calculated.

摘要翻译： 展位解码器根据展位算法对A或-A进行解码，具体取决于是否乘以AxB或-AxB。 部分乘法器/部分加法器电路30根据解码结果生成AxB或-AxB的部分乘积，并且顺序地将这些部分乘积相加。 取决于是否应该添加C，或者将C应加到乘法结果中，数据C或由C的反相比较的数据被输入到部分乘法器/部分加法器电路30。 此外，由部分乘法器/部分加法器电路30顺序地将数据C或由C的反相比较的数据相加。最后的加法器电路50执行这些部分乘积的最终加法，并且当应该加上-C时加上1。 因此，可以计算Z =±（AxB）±C（符号的顺序是可变的）。