公开(公告)号：US08791892B2

公开(公告)日：2014-07-29

申请号：US13312707

申请日：2011-12-06

Applicant: Minki Kim ,  Jinsung Kim ,  Hayoung Ji

Inventor： Minki Kim ,  Jinsung Kim ,  Hayoung Ji

IPC: G09G3/36

CPC classification number: G09G3/3648 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0439 ,  G09G2310/0297

Abstract: A liquid crystal display includes a liquid crystal display panel having a pixel array including a first group of liquid crystal cells connected to odd-numbered gate lines and a second group of liquid crystal cells connected to even-numbered gate lines and a data driving circuit including a latch array. Each liquid crystal cell of the second group shares a data line with one liquid crystal cell of the first group adjacent to the liquid crystal cell of the second group in an extension direction of the gate lines. The latch array delays only second group data to be applied to the liquid crystal cells of the second group among digital video data for one horizontal line by about one half horizontal period in response to a data rendering control signal.

Abstract translation: 液晶显示器包括具有像素阵列的液晶显示面板，该像素阵列包括连接到奇数编号的栅极线的第一组液晶单元和连接到偶数栅极线的第二组液晶单元，以及数据驱动电路， 一个锁存阵列。 第二组的每个液晶单元在栅极线的延伸方向上共享与第一组的液晶单元相邻的一个液晶单元的数据线。 响应于数据呈现控制信号，锁存器阵列仅延迟用于一个水平行的数字视频数据中施加到第二组的液晶单元的第二组数据延迟大约一半的水平周期。

公开(公告)号：US08941632B2

公开(公告)日：2015-01-27

申请号：US13305903

申请日：2011-11-29

Applicant: Minki Kim ,  Jinsung Kim ,  Hayoung Ji

Inventor： Minki Kim ,  Jinsung Kim ,  Hayoung Ji

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297 ,  G09G2330/022 ,  G09G2330/023 ,  G09G2370/08

Abstract: The present invention provides a LCD device including: a timing control unit; an oscillator which is included in the timing control unit and generates a clock frequency; a frequency divider which is included in the timing control unit and reduces the clock frequency supplied from the oscillator by dividing the clock frequency by at least 2; and a mode selection part which is included in the timing control unit and changes at least one driving mode of internal logic circuits by using the divided clock frequency supplied from the frequency divider.

Abstract translation: 本发明提供一种LCD装置，包括：定时控制单元; 包括在定时控制单元中并产生时钟频率的振荡器; 包括在定时控制单元中的分频器，并且通过将时钟频率除以至少2来减小从振荡器提供的时钟频率; 以及包括在定时控制单元中的模式选择部分，并且通过使用从分频器提供的分频时钟频率来改变内部逻辑电路的至少一个驱动模式。

公开(公告)号：US20120133628A1

公开(公告)日：2012-05-31

申请号：US13305903

申请日：2011-11-29

Applicant: Minki KIM ,  Jinsung Kim ,  Hayoung Ji

Inventor： Minki KIM ,  Jinsung Kim ,  Hayoung Ji

IPC: G09G3/36 ,  G06F3/038

CPC classification number: G09G3/3677 ,  G09G3/3614 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0297 ,  G09G2330/022 ,  G09G2330/023 ,  G09G2370/08

Abstract: The present invention provides a LCD device including: a timing control unit; an oscillator which is included in the timing control unit and generates a clock frequency; a frequency divider which is included in the timing control unit and reduces the clock frequency supplied from the oscillator by dividing the clock frequency by at least 2; and a mode selection part which is included in the timing control unit and changes at least one driving mode of internal logic circuits by using the divided clock frequency supplied from the frequency divider.

Abstract translation: 本发明提供一种LCD装置，包括：定时控制单元; 包括在定时控制单元中并产生时钟频率的振荡器; 包括在定时控制单元中的分频器，并且通过将时钟频率除以至少2来减小从振荡器提供的时钟频率; 以及包括在定时控制单元中的模式选择部分，并且通过使用从分频器提供的分频时钟频率来改变内部逻辑电路的至少一个驱动模式。

公开(公告)号：US20120146963A1

公开(公告)日：2012-06-14

申请号：US13312707

申请日：2011-12-06

Applicant: Minki Kim ,  Jinsung Kim ,  Hayoung Ji

Inventor： Minki Kim ,  Jinsung Kim ,  Hayoung Ji

IPC: G09G5/00 ,  G09G3/36

CPC classification number: G09G3/3648 ,  G09G3/3688 ,  G09G2300/0426 ,  G09G2300/0439 ,  G09G2310/0297

Abstract: A liquid crystal display includes a liquid crystal display panel having a pixel array including a first group of liquid crystal cells connected to odd-numbered gate lines and a second group of liquid crystal cells connected to even-numbered gate lines and a data driving circuit including a latch array. Each liquid crystal cell of the second group shares a data line with one liquid crystal cell of the first group adjacent to the liquid crystal cell of the second group in an extension direction of the gate lines. The latch array delays only second group data to be applied to the liquid crystal cells of the second group among digital video data for one horizontal line by about one half horizontal period in response to a data rendering control signal.

Abstract translation: 液晶显示器包括具有像素阵列的液晶显示面板，该像素阵列包括连接到奇数编号的栅极线的第一组液晶单元和连接到偶数栅极线的第二组液晶单元，以及数据驱动电路， 一个锁存阵列。 第二组的每个液晶单元在栅极线的延伸方向上共享与第一组的液晶单元相邻的一个液晶单元的数据线。 响应于数据呈现控制信号，锁存器阵列仅延迟用于一个水平行的数字视频数据中施加到第二组的液晶单元的第二组数据延迟大约一半的水平周期。

公开(公告)号：US20100066726A1

公开(公告)日：2010-03-18

申请号：US12318208

申请日：2008-12-23

Applicant: Jinsung Kim ,  Hayoung Ji

Inventor： Jinsung Kim ,  Hayoung Ji

IPC: G06F3/038

CPC classification number: G09G3/3648 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2360/18

Abstract: A display device including a display panel having a plurality of data lines and a plurality of gate lines disposed cross-wisely, a timing controller, the timing controller including a data comparing and blank time detecting device comparing whether current data and previous data are same and detecting a blank time in which no data inputs to generate a flag signal for indicating the blank time and a data keeping time in which a data same with the previous data is inputted, a memory control signal generator generating a memory clock, and stopping the generation of the memory clock when the flag signal is generated, a memory which is operated by the memory clock intermittently by the flag signal, and a data synchronizer delaying the data in time for treating operation of the data comparing and blank time detecting device and the memory control signal generator to synchronize the data inputted to the memory with the memory clock, and a data drive circuit converting data from the memory into a data voltage and supplying to the data lines, and a gate drive circuit supplying a scan pulse to the gate lines.

Abstract translation: 一种显示装置，包括具有多条数据线的显示面板和交叉设置的多条栅极线，定时控制器，所述定时控制器包括比较当前数据和先前数据是否相同的数据比较和空白时间检测装置， 检测不产生用于指示空白时间的标志信号的数据输入和其中输入与先前数据相同的数据的数据保持时间的空白时间，存储器控制信号发生器产生存储器时钟并停止生成 产生标志信号时的存储器时钟，由存储器时钟间歇地由标志信号操作的存储器和数据同步器及时延迟数据，以处理数据比较和空白时间检测装置和存储器的操作 控制信号发生器使输入到存储器的数据与存储器时钟同步，数据驱动电路从存储器int转换数据 o数据电压并提供给数据线;以及栅极驱动电路，向栅极线提供扫描脉冲。

公开(公告)号：US08089444B2

公开(公告)日：2012-01-03

申请号：US12318208

申请日：2008-12-23

Applicant: Jingsung Kim ,  Hayoung Ji

Inventor： Jingsung Kim ,  Hayoung Ji

IPC: G09G3/36

CPC classification number: G09G3/3648 ,  G09G2310/08 ,  G09G2330/021 ,  G09G2360/18

Abstract: A display device including a display panel having a plurality of data lines and a plurality of gate lines disposed cross-wisely, a timing controller, the timing controller including a data comparing and blank time detecting device comparing whether current data and previous data are same and detecting a blank time in which no data inputs to generate a flag signal for indicating the blank time and a data keeping time in which a data same with the previous data is inputted, a memory control signal generator generating a memory clock, and stopping the generation of the memory clock when the flag signal is generated, a memory which is operated by the memory clock intermittently by the flag signal, and a data synchronizer delaying the data in time for treating operation of the data comparing and blank time detecting device and the memory control signal generator to synchronize the data inputted to the memory with the memory clock, and a data drive circuit converting data from the memory into a data voltage and supplying to the data lines, and a gate drive circuit supplying a scan pulse to the gate lines.

Abstract translation: 一种显示装置，包括具有多条数据线的显示面板和交叉设置的多条栅极线，定时控制器，所述定时控制器包括比较当前数据和先前数据是否相同的数据比较和空白时间检测装置， 检测不产生用于指示空白时间的标志信号的数据输入和其中输入与先前数据相同的数据的数据保持时间的空白时间，存储器控制信号发生器产生存储器时钟并停止生成 产生标志信号时的存储器时钟，由存储器时钟间歇地由标志信号操作的存储器和数据同步器及时延迟数据，以处理数据比较和空白时间检测装置和存储器的操作 控制信号发生器使输入到存储器的数据与存储器时钟同步，数据驱动电路从存储器int转换数据 o数据电压并提供给数据线;以及栅极驱动电路，向栅极线提供扫描脉冲。