公开(公告)号：US4990801A

公开(公告)日：1991-02-05

申请号：US366830

申请日：1989-06-15

Applicant: Knut Caesar ,  Helmut Haeringer

Inventor： Knut Caesar ,  Helmut Haeringer

IPC: G11C7/22 ,  H03K5/14 ,  H03K19/177

CPC classification number: H03K5/14 ,  G11C7/22 ,  H03K19/1772

Abstract: A programmable logic array implemented with complementary insulated-gate field effect transistor technology and formed on a substrate employing a standard AND-OR structure and two non-overlapping clock phases uses diffused capacitors in a dummy row to model the worst case evaluation time of minterms in the AND plane, and a NOR gate, responsive to the dummy row, for enabling the OR plane to sum the minterms generated by the AND plane.

Abstract translation: 使用互补绝缘栅场效应晶体管技术实现的可编程逻辑阵列并且在采用标准AND-OR结构和两个非重叠时钟相位的基板上形成，在虚拟行中使用扩散电容器来模拟最坏情况下的最小化时间 AND平面和NOR门，响应于虚拟行，以使OR平面能与AND平面产生的微分相加。