公开(公告)号：US5280584A

公开(公告)日：1994-01-18

申请号：US614777

申请日：1990-11-05

Applicant: Knut Caesar ,  Ulrich Schmidt ,  Thomas Himmel ,  Arnold Uhlenhoff

Inventor： Knut Caesar ,  Ulrich Schmidt ,  Thomas Himmel ,  Arnold Uhlenhoff

IPC: H04L13/08 ,  G06F5/10 ,  G06F5/14 ,  G06F13/42 ,  G06F1/00

CPC classification number: G06F5/10 ,  G06F13/4213

Abstract: A two-way data transfer device for the data interface between two data-exchanging cells including a data source and a data sink with at least one buffer provided in each cell. When the transmitter buffer is full or the receiver buffer is empty, a backward cell stop signal freezes the state of the data source or the data sink and the cell stop signals are controlled by status signals from the respective buffers.

Abstract translation: 用于两个数据交换单元（z1，z2）的数据接口的双向数据传输设备（=握手端口），每个数据交换单元在每种情况下都包含数据源（dq）和数据宿（ds）。 为了及时缓冲数据传输，每个数据方向至少使用一个锁存器（f1，f2）。 当发送器锁存器f1已满或接收器锁存器（f2）为空时，向后单元停止信号（st1）或分别为正向信元停止信号（st2）使数据源（dq）或数据源 sink（ds）处于当前数据状态。 这些单元停止信号（st1，st2）由来自相应的锁存器（f1，f2）的附加状态信号（v2，e2）控制。

公开(公告)号：US6133767A

公开(公告)日：2000-10-17

申请号：US558670

申请日：1995-11-16

Applicant: Knut Caesar ,  Norbert Greitschus

Inventor： Knut Caesar ,  Norbert Greitschus

IPC: H03M1/12 ,  H03K5/02 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0185 ,  H03K3/00

CPC classification number: H03K19/00384 ,  H03K19/018585 ,  H03K5/02

Abstract: An integrated driver circuit for driving different capacitive loads, which includes a setting element. The setting element develops a setting signal S for a given numerical measure signal M. The numerical measure signal M is developed by an input device, which is coupled to the setting element. The numerical measure signal M corresponds to one of the different capacitive loads which is driven by the driver circuit. Coupled to the setting element is an output stage, which provides an output current that corresponds to the setting signal S.

Abstract translation: 一种用于驱动不同容性负载的集成驱动电路，其包括设定元件。 设定元件对于给定的数字测量信号M产生设定信号S.数字测量信号M由耦合到设定元件的输入设备展开。 数字测量信号M对应于由驱动器电路驱动的不同容性负载之一。 耦合到设置元件是输出级，其提供对应于设置信号S的输出电流。

公开(公告)号：US5410723A

公开(公告)日：1995-04-25

申请号：US64781

申请日：1993-05-21

Applicant: Ulrich Schmidt ,  Knut Caesar

Inventor： Ulrich Schmidt ,  Knut Caesar

IPC: G06F15/16 ,  G06F15/167 ,  G06F15/173 ,  G06F15/80 ,  G06F3/00 ,  G06F13/12 ,  G06F13/14 ,  G06F13/38

CPC classification number: G06F15/17368 ,  G06F15/17337 ,  G06F15/8023

Abstract: A wavefront array processor where each cell includes a handshake port for asynchronous data transfer with an adjacent cell. The handshake port includes a buffer for receiving data from the adjacent cell and a latch for transferring data to the adjacent cell. Data transfer is accomplished through use of a handshaking protocol which indicates whether or not a receiving buffer is full and if the buffer can receive data. Data can only be transferred if there is room in the buffer to accept the data. The handshaking protocol responds to status signals. A source status signal indicates that a data source has generated a data word. A sink status signal indicates that the buffer can receive data. Each cell further includes a data processing unit, which provides the latch with data and which accesses data from the buffer, and a blocking device, which allows the data processing unit or another handshake port to transfer data to the latch and the buffer to accept data, only when the handshake signals are appropriate. Internal to each cell is a ring bus configuration for distribution of data between the handshake ports and the data processing unit.

Abstract translation: 波阵列处理器，其中每个单元包括用于与相邻单元进行异步数据传输的握手端口。 握手端口包括用于从相邻小区接收数据的缓冲器和用于将数据传送到相邻小区的锁存器。 数据传输是通过使用一个指示接收缓冲区是否已满的握手协议来实现的，以及缓冲区是否可以接收数据。 数据只能在缓冲区有空间接受数据时传送。 握手协议响应状态信号。 源状态信号表示数据源已经生成了数据字。 接收器状态信号表示缓冲器可以接收数据。 每个单元还包括一个数据处理单元，其向锁存器提供数据并从缓冲器中访问数据，以及阻塞装置，其允许数据处理单元或另一个握手端口将数据传送到锁存器和缓冲器以接受数据 ，只有当握手信号适当时。 每个单元的内部是用于在握手端口和数据处理单元之间分配数据的环形总线配置。

公开(公告)号：US6137538A

公开(公告)日：2000-10-24

申请号：US970945

申请日：1997-11-14

Applicant: Knut Caesar ,  Manfred Juenke ,  Stefan Keller ,  Stefan Rohrer ,  Thomas Himmel ,  Kai Scheffer ,  Eric Schidlack

Inventor： Knut Caesar ,  Manfred Juenke ,  Stefan Keller ,  Stefan Rohrer ,  Thomas Himmel ,  Kai Scheffer ,  Eric Schidlack

IPC: H04N7/08 ,  H04N5/44 ,  H04N7/081 ,  H04N7/52 ,  H04N5/445 ,  H04N5/46 ,  H04N7/00

CPC classification number: H04N21/4348 ,  H04N21/4302 ,  H04N5/4401

Abstract: Bus system (1, 2, 3) for a television signal processing device for transferring video data (d8) of at least one video data source (8) and/or supplementary data (d10) of one or more supplementary-data sources (10) between a transmitter (1) and a receiver (3) by means of a bus (2), wherein at the transmitter end (1), a single data stream (d2) for the bus (2) is formed from the video (d8) and/or supplementary data (d10) by means of an interface circuit (4). The interface circuit (4) combines the video and/or supplementary data, source by source, into blocks (db; db1, db2) following each other successively in time and containing identification data (dk; sk, ik) for start and end, or start and length, and content identification, and transfers the blocks serially.

Abstract translation: 一种用于传送至少一个视频数据源（8）和/或一个或多个补充数据源（10）的视频数据（d8）和/或辅助数据（d10）的视频数据（d8）的电视信号处理装置的总线系统（1,2,3） ）通过总线（2）在发射机（1）和接收机（3）之间，其中在发射机端（1），用于总线（2）的单个数据流（d2）由视频（ d8）和/或辅助数据（d10）。 接口电路（4）将来自源的视频和/或补充数据在时间上相继连续并包含用于开始和结束的识别数据（dk; sk，ik）的块（db; db1，db2） 或开始和长度以及内容标识，并且顺序地传送块。

公开(公告)号：US4990801A

公开(公告)日：1991-02-05

申请号：US366830

申请日：1989-06-15

Applicant: Knut Caesar ,  Helmut Haeringer

Inventor： Knut Caesar ,  Helmut Haeringer

IPC: G11C7/22 ,  H03K5/14 ,  H03K19/177

CPC classification number: H03K5/14 ,  G11C7/22 ,  H03K19/1772

Abstract: A programmable logic array implemented with complementary insulated-gate field effect transistor technology and formed on a substrate employing a standard AND-OR structure and two non-overlapping clock phases uses diffused capacitors in a dummy row to model the worst case evaluation time of minterms in the AND plane, and a NOR gate, responsive to the dummy row, for enabling the OR plane to sum the minterms generated by the AND plane.

Abstract translation: 使用互补绝缘栅场效应晶体管技术实现的可编程逻辑阵列并且在采用标准AND-OR结构和两个非重叠时钟相位的基板上形成，在虚拟行中使用扩散电容器来模拟最坏情况下的最小化时间 AND平面和NOR门，响应于虚拟行，以使OR平面能与AND平面产生的微分相加。