公开(公告)号：US08533563B2

公开(公告)日：2013-09-10

申请号：US12059796

申请日：2008-03-31

Applicant: Michael Scheppler ,  Helmut Schwalm ,  Doris Keitel-Schulz ,  Xavier Veredas-Ramirez ,  Detlev Richter

Inventor： Michael Scheppler ,  Helmut Schwalm ,  Doris Keitel-Schulz ,  Xavier Veredas-Ramirez ,  Detlev Richter

IPC: G11C29/00

CPC classification number: G06F12/0246 ,  G06F11/1008 ,  G06F11/1068 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/00

Abstract: A memory system having a plurality of memory cells for storing payload data and redundancy data. The memory system having a read-out circuit configured to read-out a status of the plurality of memory cells, the read-out status having payload data, redundancy data and associated reliability information. Moreover, the memory system has a data processor configured to derive the payload data from the read-out status using the reliability information.

Abstract translation: 一种具有用于存储有效载荷数据和冗余数据的多个存储单元的存储器系统。 具有读出电路的存储器系统被配置为读出多个存储器单元的状态，读出状态具有有效载荷数据，冗余数据和相关联的可靠性信息。 此外，存储器系统具有被配置为使用可靠性信息从读出状态导出有效载荷数据的数据处理器。

公开(公告)号：US20090244973A1

公开(公告)日：2009-10-01

申请号：US12059796

申请日：2008-03-31

Applicant: Michael Scheppler ,  Helmut Schwalm ,  Doris Keitel-Schulz ,  Xavier Veredas-Ramirez ,  Detlev Richter

Inventor： Michael Scheppler ,  Helmut Schwalm ,  Doris Keitel-Schulz ,  Xavier Veredas-Ramirez ,  Detlev Richter

IPC: G11C16/06

CPC classification number: G06F12/0246 ,  G06F11/1008 ,  G06F11/1068 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/00

Abstract: A memory system having a plurality of memory cells for storing payload data and redundancy data. The memory system having a read-out circuit configured to read-out a status of the plurality of memory cells, the read-out status having payload data, redundancy data and associated reliability information. Moreover, the memory system has a data processor configured to derive the payload data from the read-out status using the reliability information.

Abstract translation: 一种具有用于存储有效载荷数据和冗余数据的多个存储单元的存储器系统。 具有读出电路的存储器系统被配置为读出多个存储器单元的状态，读出状态具有有效载荷数据，冗余数据和相关联的可靠性信息。 此外，存储器系统具有被配置为使用可靠性信息从读出状态导出有效载荷数据的数据处理器。

公开(公告)号：US20090282308A1

公开(公告)日：2009-11-12

申请号：US12118560

申请日：2008-05-09

Applicant: Jan Gutsche ,  Michael Scheppler ,  Detlev Richter ,  Doris Keitel Schulz ,  Helmut Schwalm

Inventor： Jan Gutsche ,  Michael Scheppler ,  Detlev Richter ,  Doris Keitel Schulz ,  Helmut Schwalm

IPC: G06F11/07

CPC classification number: G06F11/1052 ,  G06F11/1048

Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, at least one error detection circuit, and a controller configured to control a read operation to read state information from the at least one memory cell by reading a memory cell state information bypassing the at least one error correction circuit, or by reading the memory cell state information and supplying it to the at least one error correction circuit.

Abstract translation: 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括至少一个存储单元，至少一个错误检测电路和被配置为通过读取至少绕过至少一个存储单元的存储单元状态信息来控制读取操作以从至少一个存储单元读取状态信息的控制器 一个错误校正电路，或通过读取存储单元状态信息并将其提供给至少一个纠错电路。