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公开(公告)号：US5771262A
公开(公告)日：1998-06-23
申请号：US716077
申请日：1996-09-19
摘要： The invention provides an impedance adapter that automaticaly switches to impedances that match network transmit/receive lines impedances (105,106) by a controlled switching of various impedances mounted serially/parallely with connected transmitter/receiver (100,101). For a high speed adapter, a balanced transmitter/receiver is required for limiting crosstalk effect due to the high transmission rate. Transmit/Receive impedance adaptation networks (102-103) are composed of serial/parallel networks of resistors and relay contacts that are switched independently by magnetic coils of an impedance switching circuit (110) and having values conformable to the various network impedances imposed by different national regulations. By using the principle of double deviation voltage technique, a measuring circuit (108) detects upward and downward voltages (VA,VB), VB amplified by 2 to generate an analog signal VS (VS=VA-2VB) to a control logic circuit (109). This circuit (109) determines if the resistors value selected by the magnetic coils of said impedance switching circuit (110) is equal or not equal to the impedance of the network lines (106,105). Thus, it compares VS to a voltage Vref (25) to generate an output which selects and activates the correct magnetic coil for changing or keeping equal the resistors of the receive/transmit impedance network (102,103) currently connected to the network lines (105,106).
摘要翻译： 本发明提供一种阻抗适配器，其通过与所连接的发射机/接收机（100,101）串联/并行安装的各种阻抗的受控切换，自动切换到与网络发射/接收线路阻抗（105,106）匹配的阻抗。 对于高速适配器，由于高传输速率，需要一个平衡的发射器/接收器来限制串扰效应。 发射/接收阻抗适配网络（102-103）由电阻器和继电器触点的串联/并联网络组成，其由阻抗开关电路（110）的磁线圈独立地切换，并且具有与不同的不同网络阻抗匹配的值 国家规定。 通过使用双偏压电压技术的原理，测量电路（108）检测向上和向下的电压（VA，VB），VB放大2以产生模拟信号VS（VS = VA-2VB）到控制逻辑电路 109）。 该电路（109）确定由所述阻抗开关电路（110）的磁线圈选择的电阻值是否等于网线（106,105）的阻抗。 因此，它将VS与电压Vref（25）进行比较以产生输出，该输出选择并激活正确的磁线圈，用于改变或保持与当前连接到网络线路（105,106）的接收/发射阻抗网络（102,103）的电阻相等， 。
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2.发明授权
公开(公告)号：US5519737A
公开(公告)日：1996-05-21
申请号：US48598
申请日：1993-04-19
CPC分类号： H04L7/10 , H04J3/0685 , H04L7/0331
摘要： An adapter having a line interface circuit for providing an analog attachment to a network (100). The line interface circuit is provided with a reset input for beginning a resynchronization of the timing of the adapter. The adapter further includes a Digital Phase-locked Loop device DPLL (203) driven by a master clock (306) which provides the timing and synchronization signals to the line interface circuits (201). The DPLL (203) divides a master clock down to an internal INT clock (309), a phase comparator (303) compares the INT clock with a reference signal (302) which is synchronized with the receive clock (202) extracted from the line by line interface (201). The phase comparison process operates with a Correction Signal (CS) which has a window centered around the falling edge of the INT clock. A frequency correction is initiated when the reference clock falls outside of the correction window and is achieved by inserting or suppressing a master clock pulse at this time. The adapter further includes means for resetting the line interface circuits and the DPLL at the power-on of the adapter, such that the frequency correction apparatus of the adapter causes two adapters attached at separate ends of a transmission medium to evolve toward stable timing states with respect to each other.
摘要翻译： 具有用于向网络（100）提供模拟附件的线路接口电路的适配器。 线路接口电路设置有用于开始适配器的定时的再同步的复位输入。 适配器还包括由主时钟（306）驱动的数字锁相环装置DPLL（203），其将时序和同步信号提供给线路接口电路（201）。 DPLL（203）将主时钟下降到内部INT时钟（309），相位比较器（303）将INT时钟与与从线提取的接收时钟（202）同步的参考信号（302）进行比较 （201）。 相位比较过程使用具有以INT时钟的下降沿为中心的窗口的校正信号（CS）进行操作。 当参考时钟落在校正窗口之外时，开始频率校正，并通过插入或抑制此时的主时钟脉冲来实现。 适配器还包括用于在适配器的电源接通时复位线路接口电路和DPLL的装置，使得适配器的频率校正装置使得连接在传输介质的分离端处的两个适配器朝着稳定的定时状态演变， 相互尊重
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