公开(公告)号：US08551873B2

公开(公告)日：2013-10-08

申请号：US13610142

申请日：2012-09-11

申请人： Yusuke Onuki ,  Takehito Okabe ,  Hideaki Ishino

发明人： Yusuke Onuki ,  Takehito Okabe ,  Hideaki Ishino

IPC分类号： H01L21/28

CPC分类号： H01L21/28247 ,  H01L27/14649 ,  H01L27/14689 ,  H01L29/6656 ,  H01L29/7833

摘要： A method for manufacturing a semiconductor device having a MOS transistor, includes forming a gate electrode material layer on a first insulating film formed on a semiconductor substrate, forming an etching mask on the gate electrode material layer, forming a gate electrode by patterning the gate electrode material layer such that a protective film that protects at least a lower portion of a side face of the gate electrode and a portion of the first insulating film, which is adjacent to the side face, is formed while the gate electrode material layer is patterned, forming a second insulating film on the semiconductor substrate on which the gate electrode is formed, and forming an interlayer insulation film on the second insulating film.

摘要翻译： 一种制造具有MOS晶体管的半导体器件的方法，包括在形成在半导体衬底上的第一绝缘膜上形成栅电极材料层，在栅电极材料层上形成蚀刻掩模，通过图案化栅电极形成栅电极 材料层，使得在对栅电极材料层进行图案化的同时形成保护栅电极的侧面的至少下部和与侧面相邻的第一绝缘膜的一部分的保护膜， 在其上形成有栅电极的半导体衬底上形成第二绝缘膜，并在第二绝缘膜上形成层间绝缘膜。

公开(公告)号：US20130089975A1

公开(公告)日：2013-04-11

申请号：US13610142

申请日：2012-09-11

申请人： Yusuke Onuki ,  Takehito Okabe ,  Hideaki Ishino

发明人： Yusuke Onuki ,  Takehito Okabe ,  Hideaki Ishino

IPC分类号： H01L21/28

CPC分类号： H01L21/28247 ,  H01L27/14649 ,  H01L27/14689 ,  H01L29/6656 ,  H01L29/7833

摘要： A method for manufacturing a semiconductor device having a MOS transistor, includes forming a gate electrode material layer on a first insulating film formed on a semiconductor substrate, forming an etching mask on the gate electrode material layer, forming a gate electrode by patterning the gate electrode material layer such that a protective film that protects at least a lower portion of a side face of the gate electrode and a portion of the first insulating film, which is adjacent to the side face, is formed while the gate electrode material layer is patterned, forming a second insulating film on the semiconductor substrate on which the gate electrode is formed, and forming an interlayer insulation film on the second insulating film.

摘要翻译： 一种制造具有MOS晶体管的半导体器件的方法，包括在形成在半导体衬底上的第一绝缘膜上形成栅电极材料层，在栅电极材料层上形成蚀刻掩模，通过图案化栅电极形成栅电极 材料层，使得在对栅电极材料层进行图案化的同时形成保护栅电极的侧面的至少下部和与侧面相邻的第一绝缘膜的一部分的保护膜， 在其上形成有栅电极的半导体衬底上形成第二绝缘膜，并在第二绝缘膜上形成层间绝缘膜。