公开(公告)号：US08502560B2

公开(公告)日：2013-08-06

申请号：US13235953

申请日：2011-09-19

Applicant: Takashi Taguchi ,  Hiroyuki Ideno

Inventor： Takashi Taguchi ,  Hiroyuki Ideno

IPC: H03K19/0175

CPC classification number: H03K19/018521 ,  H03K3/35613 ,  H03K19/09429

Abstract: An output circuit which outputs an output signal based on an input signal from an output terminal and brings the output terminal into a high impedance state in response to an impedance control signal. The output circuit includes an output pMOS transistor connected at a source thereof to a first power supply. The output circuit includes an output nMOS transistor connected between a drain of the output pMOS transistor and ground. The output circuit includes an output terminal connected between the drain of the output pMOS transistor and a drain of the output nMOS transistor. The output circuit includes a first level shifter circuit which outputs a first gate control signal from a first gate control terminal to control on/off of the output pMOS transistor. The output circuit includes a second level shifter circuit which outputs a second gate control signal from a second gate control terminal to control on/off of the output nMOS transistor.

Abstract translation: 输出电路，其根据来自输出端子的输入信号输出输出信号，并根据阻抗控制信号使输出端子成为高阻抗状态。 输出电路包括在其源极处连接到第一电源的输出pMOS晶体管。 输出电路包括连接在输出pMOS晶体管的漏极和地之间的输出nMOS晶体管。 输出电路包括连接在输出pMOS晶体管的漏极和输出nMOS晶体管的漏极之间的输出端子。 输出电路包括第一电平移位器电路，其输出来自第一栅极控制端子的第一栅极控制信号以控制输出pMOS晶体管的导通/截止。 输出电路包括第二电平移位器电路，其输出来自第二栅极控制端子的第二栅极控制信号以控制输出nMOS晶体管的导通/截止。

公开(公告)号：US20120229164A1

公开(公告)日：2012-09-13

申请号：US13235953

申请日：2011-09-19

Applicant: Takashi Taguchi ,  Hiroyuki Ideno

Inventor： Takashi Taguchi ,  Hiroyuki Ideno

IPC: H03K19/0175

CPC classification number: H03K19/018521 ,  H03K3/35613 ,  H03K19/09429

Abstract: An output circuit which outputs an output signal based on an input signal from an output terminal and brings the output terminal into a high impedance state in response to an impedance control signal. The output circuit includes an output pMOS transistor connected at a source thereof to a first power supply. The output circuit includes an output nMOS transistor connected between a drain of the output pMOS transistor and ground. The output circuit includes an output terminal connected between the drain of the output pMOS transistor and a drain of the output nMOS transistor. The output circuit includes a first level shifter circuit which outputs a first gate control signal from a first gate control terminal to control on/off of the output pMOS transistor. The output circuit includes a second level shifter circuit which outputs a second gate control signal from a second gate control terminal to control on/off of the output nMOS transistor.

Abstract translation: 输出电路，其根据来自输出端子的输入信号输出输出信号，并根据阻抗控制信号使输出端子成为高阻抗状态。 输出电路包括在其源极处连接到第一电源的输出pMOS晶体管。 输出电路包括连接在输出pMOS晶体管的漏极和地之间的输出nMOS晶体管。 输出电路包括连接在输出pMOS晶体管的漏极和输出nMOS晶体管的漏极之间的输出端子。 输出电路包括第一电平移位器电路，其输出来自第一栅极控制端子的第一栅极控制信号以控制输出pMOS晶体管的导通/截止。 输出电路包括第二电平移位器电路，其输出来自第二栅极控制端子的第二栅极控制信号以控制输出nMOS晶体管的导通/截止。