公开(公告)号：US08631809B2

公开(公告)日：2014-01-21

申请号：US12725981

申请日：2010-03-17

Applicant: Tetsuya Hamada ,  Takashi Taguchi

Inventor： Tetsuya Hamada ,  Takashi Taguchi

IPC: B08B3/00

CPC classification number: G03F7/20 ,  H01L21/67178 ,  H01L21/67225 ,  H01L21/67303 ,  H01L21/67742 ,  H01L21/67748 ,  Y10S134/902

Abstract: An interface block is constituted by a cleaning/drying processing block and a carry-in/carry-out block. The cleaning/drying processing block includes cleaning/drying processing sections and a transport section. The transport section is provided with a transport mechanism. The carry-in/carry-out block is provided with a transport mechanism. The transport mechanism carries substrates in and out of an exposure device.

Abstract translation: 接口块由清洁/干燥处理块和进/出块组成。 清洁/干燥处理块包括清洁/干燥处理部分和传送部分。 运输部分设有运输机构。 输入/输出块具有传送机构。 输送机构将基板输入和移出曝光装置。

公开(公告)号：US08502560B2

公开(公告)日：2013-08-06

申请号：US13235953

申请日：2011-09-19

Applicant: Takashi Taguchi ,  Hiroyuki Ideno

Inventor： Takashi Taguchi ,  Hiroyuki Ideno

IPC: H03K19/0175

CPC classification number: H03K19/018521 ,  H03K3/35613 ,  H03K19/09429

Abstract: An output circuit which outputs an output signal based on an input signal from an output terminal and brings the output terminal into a high impedance state in response to an impedance control signal. The output circuit includes an output pMOS transistor connected at a source thereof to a first power supply. The output circuit includes an output nMOS transistor connected between a drain of the output pMOS transistor and ground. The output circuit includes an output terminal connected between the drain of the output pMOS transistor and a drain of the output nMOS transistor. The output circuit includes a first level shifter circuit which outputs a first gate control signal from a first gate control terminal to control on/off of the output pMOS transistor. The output circuit includes a second level shifter circuit which outputs a second gate control signal from a second gate control terminal to control on/off of the output nMOS transistor.

Abstract translation: 输出电路，其根据来自输出端子的输入信号输出输出信号，并根据阻抗控制信号使输出端子成为高阻抗状态。 输出电路包括在其源极处连接到第一电源的输出pMOS晶体管。 输出电路包括连接在输出pMOS晶体管的漏极和地之间的输出nMOS晶体管。 输出电路包括连接在输出pMOS晶体管的漏极和输出nMOS晶体管的漏极之间的输出端子。 输出电路包括第一电平移位器电路，其输出来自第一栅极控制端子的第一栅极控制信号以控制输出pMOS晶体管的导通/截止。 输出电路包括第二电平移位器电路，其输出来自第二栅极控制端子的第二栅极控制信号以控制输出nMOS晶体管的导通/截止。

公开(公告)号：US20100236587A1

公开(公告)日：2010-09-23

申请号：US12725981

申请日：2010-03-17

Applicant: Tetsuya HAMADA ,  Takashi Taguchi

Inventor： Tetsuya HAMADA ,  Takashi Taguchi

IPC: B08B7/00

CPC classification number: G03F7/20 ,  H01L21/67178 ,  H01L21/67225 ,  H01L21/67303 ,  H01L21/67742 ,  H01L21/67748 ,  Y10S134/902

Abstract: An interface block is constituted by a cleaning/drying processing block and a carry-in/carry-out block. The cleaning/drying processing block includes cleaning/drying processing sections and a transport section. The transport section is provided with a transport mechanism. The carry-in/carry-out block is provided with a transport mechanism. The transport mechanism carries substrates in and out of an exposure device.

Abstract translation: 接口块由清洁/干燥处理块和进/出块组成。 清洁/干燥处理块包括清洁/干燥处理部分和传送部分。 运输部分设有运输机构。 输入/输出块具有传送机构。 输送机构将基板输入和移出曝光装置。

公开(公告)号：US20100136257A1

公开(公告)日：2010-06-03

申请号：US12698862

申请日：2010-02-02

Applicant: Shuichi Yasuda ,  Masashi Kanaoka ,  Koji Kaneyama ,  Tadashi Miyagi ,  Kazuhito Shigemori ,  Toru Asano ,  Yukio Toriyama ,  Takashi Taguchi ,  Tsuyoshi Mitsuhashi ,  Tsuyoshi Okumura

Inventor： Shuichi Yasuda ,  Masashi Kanaoka ,  Koji Kaneyama ,  Tadashi Miyagi ,  Kazuhito Shigemori ,  Toru Asano ,  Yukio Toriyama ,  Takashi Taguchi ,  Tsuyoshi Mitsuhashi ,  Tsuyoshi Okumura

IPC: B05D3/06

CPC classification number: G03F7/30 ,  H01L21/67028 ,  H01L21/67034 ,  H01L21/67051 ,  H01L21/67178 ,  H01L21/67225

Abstract: A method of processing a substrate in a substrate processing apparatus that is arranged adjacent to an exposure device and includes first, second and third processing units, includes forming a photosensitive film on the substrate by said first processing unit before exposure processing by said exposure device and applying washing processing to the substrate by supplying a washing liquid to the substrate in said second processing unit after the formation of said photosensitive film and before the exposure processing. The method also includes applying drying processing to the substrate in said second processing unit after the washing processing by said second processing unit and before the exposure processing and applying development processing to the substrate by said third processing unit after the exposure processing. Applying the drying processing to the substrate includes the step of supplying an inert gas onto the substrate, to which the washing liquid is supplied.

Abstract translation: 一种在与曝光装置相邻并且包括第一，第二和第三处理单元的基板处理装置中处理基板的方法，包括在所述曝光装置的曝光处理之前由所述第一处理单元在所述基板上形成感光膜，以及 在形成所述感光膜之后并且在所述曝光处理之前，通过在所述第二处理单元中向所述基板供应洗涤液体来向所述基板施加洗涤处理。 该方法还包括在所述第二处理单元的洗涤处理之后并且在曝光处理之前对所述第二处理单元中的基板进行干燥处理，并且在曝光处理之后，通过所述第三处理单元对基板进行显影处理。 将干燥处理应用于基板包括向供给洗涤液的基板供给惰性气体的工序。

公开(公告)号：US07549811B2

公开(公告)日：2009-06-23

申请号：US11948198

申请日：2007-11-30

Applicant: Yoshihisa Yamada ,  Masafumi Maeda ,  Takashi Taguchi

Inventor： Yoshihisa Yamada ,  Masafumi Maeda ,  Takashi Taguchi

IPC: G03D5/00 ,  G03B13/00 ,  G03B27/52 ,  B05C11/02 ,  B05B13/04

CPC classification number: H01L21/67748 ,  H01L21/67178 ,  H01L21/67225 ,  H01L21/67276 ,  Y10S414/135

Abstract: A forward direction-only path (first substrate transport path) is formed for transporting substrates in a forward direction to pass the substrates on to an exposing apparatus. A separate, substrate transport path (second substrate transport path) is formed exclusively for post-exposure bake (PEB). Substrate transport along each path is carried out independently of substrate transport along the other. A fourth main transport mechanism is interposed as a predetermined substrate transport mechanism between transfer points consisting of a buffer acting as a temporary storage module for temporarily storing the substrates and a post-exposure bake (PEB) unit corresponding to a predetermined treating unit. This arrangement forms the path for transporting the substrates between the buffer and the PEB unit, to allow PEB treatment of the substrates to be performed smoothly. Similarly, the substrates are transported smoothly to the buffer.

Abstract translation: 形成向前方向路径（第一基板输送路径），用于沿正向方向输送基板，使基板通过曝光装置。 单独的基板输送路径（第二基板输送路径）专门用于后曝光烘烤（PEB）。 沿着每个路径的基板传送独立于彼此的基板传送进行。 第四主要传送机构作为预定的基板传送机构，在由用作临时存储基板的临时存储模块的缓冲器和对应于预定处理单元的曝光后烘烤（PEB）单元组成的传送点之间。 该布置形成用于在缓冲器和PEB单元之间传送基板的路径，以允许平滑地执行基板的PEB处理。 类似地，衬底被平滑地输送到缓冲器。

公开(公告)号：US20060152694A1

公开(公告)日：2006-07-13

申请号：US11295216

申请日：2005-12-06

Applicant: Shuichi Yasuda ,  Masashi Kanaoka ,  Koji Kaneyama ,  Tadashi Miyagi ,  Kazuhito Shigemori ,  Toru Asano ,  Yukio Toriyama ,  Takashi Taguchi ,  Tsuyoshi Mitsuhashi ,  Tsuyoshi Okumura

Inventor： Shuichi Yasuda ,  Masashi Kanaoka ,  Koji Kaneyama ,  Tadashi Miyagi ,  Kazuhito Shigemori ,  Toru Asano ,  Yukio Toriyama ,  Takashi Taguchi ,  Tsuyoshi Mitsuhashi ,  Tsuyoshi Okumura

IPC: G03B27/32

CPC classification number: G03F7/30 ,  H01L21/67028 ,  H01L21/67034 ,  H01L21/67051 ,  H01L21/67178 ,  H01L21/67225

Abstract: A substrate processing apparatus comprises an indexer block, an anti-reflection film processing block, a resist film processing block, a development processing block, a washing processing block, and an interface block. An exposure device is arranged adjacent to the interface block. The washing processing block comprises washing processing group. A resist film is formed in the resist film processing block. Before the substrate is subjected to exposure processing by the exposure device, the substrate is subjected to washing and drying processing in the washing processing group.

Abstract translation: 基板处理装置包括分度器块，抗反射膜处理块，抗蚀剂膜处理块，显影处理块，洗涤处理块和接口块。 曝光装置设置在接口块附近。 洗涤处理块包括洗涤处理组。 在抗蚀剂膜处理块中形成抗蚀剂膜。 在通过曝光装置对基板进行曝光处理之前，在洗涤处理组中对基板进行洗涤和干燥处理。

公开(公告)号：US06809002B2

公开(公告)日：2004-10-26

申请号：US10154823

申请日：2002-05-28

Applicant: Sachiko Yabe ,  Takashi Taguchi

Inventor： Sachiko Yabe ,  Takashi Taguchi

IPC: H01L2762

CPC classification number: H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

Abstract: A silicon-on-insulator (SOI) substrate has a grid-line region and a circuit region, and includes a silicon substrate having an upper surface, a first insulating layer having an upper surface and a silicon layer, and which has a grid-line region zoning a circuit region. An element isolation region is formed in the silicon layer of the circuit region of the SOI substrate, and an insulating region is formed in the silicon layer of the grid-line region of the SOI substrate. The insulating region and a portion of the first insulating layer located under the insulating region are removed to define a recess in the grid-line region.

Abstract translation: 绝缘体上硅（SOI）衬底具有网格线区域和电路区域，并且包括具有上表面的硅衬底，具有上表面和硅层的第一绝缘层， 线区域划分电路区域。 在SOI衬底的电路区域的硅层中形成元件隔离区域，并且在SOI衬底的栅格区域的硅层中形成绝缘区域。 绝缘区域和位于绝缘区域下方的第一绝缘层的一部分被去除以在网格线区域中限定凹陷。

公开(公告)号：US06549196B1

公开(公告)日：2003-04-15

申请号：US09401847

申请日：1999-09-22

Applicant: Takashi Taguchi ,  Takeshi Shima ,  Tetsuro Itakura

Inventor： Takashi Taguchi ,  Takeshi Shima ,  Tetsuro Itakura

IPC: B09G500

CPC classification number: H03M1/0872 ,  G09G3/3688 ,  G09G2310/027 ,  H03M1/765

Abstract: A D/A conversion circuit which can perform D/A conversion at high speed and with high precision is disclosed. The D/A conversion circuit comprises an analog reference power supply, an output buffer, a multiplexer, a pre-buffer, and a current changeover switch. The pre-buffer operates with a power supply voltage different from that of the analog reference power supply, and outputs a voltage substantially equal to an output voltage of the analog reference power supply. For a predetermined period after logic of digital data changes, the output voltage of the pre-buffer is supplied to the output buffer, and an input parasitic capacitor of the output buffer is charged/discharged. After the predetermined period elapses, the output voltage of the analog reference power supply is supplied to the output buffer. Therefore, a charging/discharging current of the input parasitic capacitor does not flow through the analog reference power supply, and fluctuation of the output voltage of the analog reference power supply can be suppressed.

Abstract translation: 公开了一种可以高速，高精度地执行D / A转换的D / A转换电路。 D / A转换电路包括模拟参考电源，输出缓冲器，多路复用器，预缓冲器和电流切换开关。 预缓冲器以与模拟基准电源不同的电源电压工作，并输出基本上等于模拟基准电源的输出电压的电压。 在数字数据的逻辑变化之后的预定时间内，预缓冲器的输出电压被提供给输出缓冲器，并且输出缓冲器的输入寄生电容器被充电/放电。 经过预定时间后，模拟基准电源的输出电压被提供给输出缓冲器。 因此，输入的寄生电容器的充电/放电电流不会流过模拟基准电源，并且可以抑制模拟基准电源的输出电压的波动。

公开(公告)号：US6111404A

公开(公告)日：2000-08-29

申请号：US13257

申请日：1998-01-26

Applicant: Masahiko Tashiro ,  Takashi Taguchi

Inventor： Masahiko Tashiro ,  Takashi Taguchi

IPC: G01P3/488 ,  G01B7/14 ,  G01D5/245

CPC classification number: G01P3/488 ,  F16H55/36 ,  G01D5/24438 ,  F16H2055/366

Abstract: A detected projection is integrally provided on one side of a rotor produced by pressing a plate material. A portion of a rotor is allowed to bulge from one side of the rotor by pressing. At least one end of the projection in a circumferential direction of the rotor is comprised of a shear end face steeply rising from the side of the rotor by a shearing effect during pressing. The shear end face is formed as a sensing end face for an electromagnetic pick-up. The detected projection generates a rotation detecting pulse in an electromagnetic pick-up disposed in proximity to the rotor. The accuracy in size of the projection is enhanced and moreover, when the projection is detected by the electromagnetic pick-up, a pulse wave form is generated clearly and sharply, thereby enhancing the sensing accuracy.

Abstract translation: 在通过压制板材制造的转子的一侧上一体地设置检测的突起。 转子的一部分允许通过按压从转子的一侧凸出。 在转子的圆周方向上的突起的至少一个端部由在压制期间通过剪切效应从转子侧急剧上升的剪切端面构成。 剪切端面形成为用于电磁拾取器的感测端面。 检测到的投影在靠近转子设置的电磁拾取器中产生旋转检测脉冲。 提高投影尺寸的精度，而且，当通过电磁拾波器检测到投影时，产生清晰而清晰的脉搏波形，从而提高感测精度。

公开(公告)号：US5449928A

公开(公告)日：1995-09-12

申请号：US120379

申请日：1993-09-14

Applicant: Kazuoki Matsugatani ,  Takashi Taguchi ,  Yoshiki Ueno ,  Tadashi Hattori

Inventor： Kazuoki Matsugatani ,  Takashi Taguchi ,  Yoshiki Ueno ,  Tadashi Hattori

IPC: H01L29/812 ,  H01L21/338 ,  H01L29/205 ,  H01L29/778 ,  H01L29/64

CPC classification number: H01L29/7783 ,  H01L29/205

Abstract: A pseudomorphic HEMT of a structure which prevents the distribution of 2DEG in the channel layer from being concentrated near the hetero-interface relative to a doping layer and which, at the same time, enables the thickness of the channel layer to which distortion is imparted to be decreased. In an n-InAlAs/InGaAs pseudomorphic structure grown on an InP substrate 1, an InGaAs spacer layer 4 having an In composition ratio smaller than that of an InGaAs channel layer 3 is inserted in an InAlAs/InGaAs hetero-interface. The InGaAs channel layer 3 has an In composition ratio of 0.80 to exhibit a high mobility. Another InAlAs buffer layer 2, spacer layer 5 and doping layer 6 have an In composition ratio of 0.52 which is in lattice-match with the substrate, and InGaAs spacer layer 4 and cap layer 7 have an In composition ratio of 0.53 which is in lattice-match with the substrate. This constitution makes it possible to control the two-dimensional electron gas and to further increase the mobility.

Abstract translation: 阻止2DEG在沟道层中的分布的伪形HEMT相对于掺杂层被集中在异质界面附近，并且同时使得能够使畸变被赋予的沟道层的厚度 减少 在InP衬底1上生长的n-InAlAs / InGaAs伪晶体结构中，In InAs / InGaAs异质界面中插入具有小于InGaAs沟道层3的In组成比的InGaAs间隔层4。 InGaAs沟道层3的In组成比为0.80，具有高迁移率。 另一种InAlAs缓冲层2，间隔层5和掺杂层6的In组成比为0.52，与衬底晶格匹配，InGaAs间隔层4和覆盖层7的In组成比为0.53，晶格 - 与底物匹配。 这种结构使得可以控制二维电子气并进一步提高迁移率。