公开(公告)号：US5543334A

公开(公告)日：1996-08-06

申请号：US356419

申请日：1994-12-15

申请人： Ichiro Yoshii ,  Hiroyuki Kamijoh ,  Yoshio Ozawa ,  Kikuo Yamabe ,  Kazuhiko Hashimoto ,  Katsuya Okumura ,  Kaoru Hama

发明人： Ichiro Yoshii ,  Hiroyuki Kamijoh ,  Yoshio Ozawa ,  Kikuo Yamabe ,  Kazuhiko Hashimoto ,  Katsuya Okumura ,  Kaoru Hama

IPC分类号： H01L21/66

CPC分类号： H01L22/14 ,  H01L2924/0002

摘要： A method of screening a semiconductor device. A silicon wafer having gate electrodes formed on the gate oxide film is prepared. An insulating layer is deposited on the silicon wafer. Gate electrode portions of a group of transistors to be tested are exposed. A conductive layer is deposited on the silicon wafer having exposed gate electrodes. The conductive layer is patterned to be a wiring layer so that the gate electrodes of a group of the transistors can be electrically connected to each other. The chip area to be tested is irradiated with light having intensity enough to generate a required quantity of carriers in a depletion layer between a well and a substrate. A predetermined test voltage is applied between the wiring layer and the substrate of the silicon wafer during irradiation of the light to measure current flowing through the wiring layer and the gate oxide film. An abnormality of the gate oxide film can be detected on the basis of the measured current value. The screening method may be conducted before the completion of forming the gate electrodes. Further, gate electrode portions not to be used by a user may not be electrically connected to the gate electrode portions to be used.

摘要翻译： 一种半导体器件的屏蔽方法。 制备在栅氧化膜上形成栅电极的硅晶片。 绝缘层沉积在硅晶片上。 待测试的一组晶体管的栅电极部分露出。 在具有暴露的栅电极的硅晶片上沉积导电层。 导电层被图案化为布线层，使得一组晶体管的栅电极可以彼此电连接。 用足够强度的光照射要测试的芯片面积，以在阱和衬底之间的耗尽层中产生所需量的载流子。 在光照射期间，在布线层和硅晶片的基板之间施加预定的测试电压，以测量流过布线层和栅氧化膜的电流。 可以基于测量的电流值来检测栅氧化膜的异常。 筛选方法可以在形成栅电极的完成之前进行。 此外，用户不使用的栅电极部分可以不与要使用的栅电极部分电连接。