公开(公告)号：US5682059A

公开(公告)日：1997-10-28

申请号：US712156

申请日：1996-09-12

Applicant: Ichiro Yoshii ,  Mariko Takagi

Inventor： Ichiro Yoshii ,  Mariko Takagi

IPC: H01L21/82 ,  H01L21/78 ,  H01L23/525 ,  H01L27/10 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: In a semiconductor device including an anti-fuse element, a first electrode layer is formed on a semiconductor substrate. A first insulating layer is formed only on the first electrode layer for insulating the first electrode layer. An anti-fuse insulating film is coated on at least one side wall portion of each of the first electrode layer and the first insulating layer. A second electrode layer is formed on the anti-fuse insulating film, and the first and second electrode layers and the anti-fuse insulating film constitute the anti-fuse element.

Abstract translation: 在包括反熔丝元件的半导体器件中，在半导体衬底上形成第一电极层。 第一绝缘层仅形成在第一电极层上，用于绝缘第一电极层。 在第一电极层和第一绝缘层的至少一个侧壁部分上涂布抗熔丝绝缘膜。 第二电极层形成在反熔丝绝缘膜上，第一和第二电极层和反熔丝绝缘膜构成反熔丝元件。

公开(公告)号：US5670816A

公开(公告)日：1997-09-23

申请号：US487163

申请日：1995-06-07

Applicant: Hiroshi Hatano ,  Ichiro Yoshii ,  Satoru Takatsuka

Inventor： Hiroshi Hatano ,  Ichiro Yoshii ,  Satoru Takatsuka

IPC: H01L27/118 ,  H01L29/76

CPC classification number: H01L27/11807

Abstract: In a semiconductor device having at least two conductive layers disposed close to each other on an element isolating insulation film formed on a first P-type region, a second P-type region is formed in a region of the first P-type region which is between the two conductive layers. The impurity concentration of the second P-type diffusion region is higher than the first P-type region. A region of the element isolating insulation film which is on the second P-type diffusion region is thin to form a thin insulation film. With the features, no inversion layer is formed in the region of the first P-type region where the second P-type diffusion region is formed. As a result, the inversion layers under the conductive layers will not be in contact with each other.

Abstract translation: 在形成在第一P型区域上的元件隔离绝缘膜上具有至少两个彼此靠近配置的导电层的半导体器件中，在第一P型区域的区域形成第二P型区域， 在两个导电层之间。 第二P型扩散区域的杂质浓度高于第一P型区域。 位于第二P型扩散区域上的元件隔离绝缘膜的区域薄，形成薄的绝缘膜。 具有这样的特征，在形成第二P型扩散区域的第一P型区域的区域中不形成反转层。 结果，导电层下的反转层将不会彼此接触。

公开(公告)号：US5929505A

公开(公告)日：1999-07-27

申请号：US522654

申请日：1995-09-01

Applicant: Mariko Takagi ,  Ichiro Yoshii

Inventor： Mariko Takagi ,  Ichiro Yoshii

IPC: H01L21/3205 ,  H01L21/768 ,  H01L21/82 ,  H01L23/52 ,  H01L23/522 ,  H01L23/525 ,  H01L27/10 ,  H01L29/00

CPC classification number: H01L21/76886 ,  H01L23/5252 ,  H01L2924/0002

Abstract: A first electrode layer is formed on a semiconductor substrate, and surfaces other than a top surface thereof are buried in an insulation film, and the top surface makes the same surface as that of the insulation film. An antifuse insulation film is formed on a flat surface including the top surface of the first electrode layer. A second electrode layer is formed on the antifuse insulation film. An antifuse portion is formed by self-alignment at a cross point between the first and second electrode layers.

Abstract translation: 第一电极层形成在半导体衬底上，并且除了顶表面之外的表面被埋在绝缘膜中，并且顶表面与绝缘膜的表面相同。 在包括第一电极层的顶表面的平坦表面上形成反熔丝绝缘膜。 第二电极层形成在反熔丝绝缘膜上。 通过在第一和第二电极层之间的交叉点处的自对准形成反熔丝部分。

公开(公告)号：US5543334A

公开(公告)日：1996-08-06

申请号：US356419

申请日：1994-12-15

Applicant: Ichiro Yoshii ,  Hiroyuki Kamijoh ,  Yoshio Ozawa ,  Kikuo Yamabe ,  Kazuhiko Hashimoto ,  Katsuya Okumura ,  Kaoru Hama

Inventor： Ichiro Yoshii ,  Hiroyuki Kamijoh ,  Yoshio Ozawa ,  Kikuo Yamabe ,  Kazuhiko Hashimoto ,  Katsuya Okumura ,  Kaoru Hama

IPC: H01L21/66

CPC classification number: H01L22/14 ,  H01L2924/0002

Abstract: A method of screening a semiconductor device. A silicon wafer having gate electrodes formed on the gate oxide film is prepared. An insulating layer is deposited on the silicon wafer. Gate electrode portions of a group of transistors to be tested are exposed. A conductive layer is deposited on the silicon wafer having exposed gate electrodes. The conductive layer is patterned to be a wiring layer so that the gate electrodes of a group of the transistors can be electrically connected to each other. The chip area to be tested is irradiated with light having intensity enough to generate a required quantity of carriers in a depletion layer between a well and a substrate. A predetermined test voltage is applied between the wiring layer and the substrate of the silicon wafer during irradiation of the light to measure current flowing through the wiring layer and the gate oxide film. An abnormality of the gate oxide film can be detected on the basis of the measured current value. The screening method may be conducted before the completion of forming the gate electrodes. Further, gate electrode portions not to be used by a user may not be electrically connected to the gate electrode portions to be used.

Abstract translation: 一种半导体器件的屏蔽方法。 制备在栅氧化膜上形成栅电极的硅晶片。 绝缘层沉积在硅晶片上。 待测试的一组晶体管的栅电极部分露出。 在具有暴露的栅电极的硅晶片上沉积导电层。 导电层被图案化为布线层，使得一组晶体管的栅电极可以彼此电连接。 用足够强度的光照射要测试的芯片面积，以在阱和衬底之间的耗尽层中产生所需量的载流子。 在光照射期间，在布线层和硅晶片的基板之间施加预定的测试电压，以测量流过布线层和栅氧化膜的电流。 可以基于测量的电流值来检测栅氧化膜的异常。 筛选方法可以在形成栅电极的完成之前进行。 此外，用户不使用的栅电极部分可以不与要使用的栅电极部分电连接。

公开(公告)号：US5192988A

公开(公告)日：1993-03-09

申请号：US728532

申请日：1991-07-11

Applicant: Ichiro Yoshii

Inventor： Ichiro Yoshii

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/336 ,  H01L21/768 ,  H01L27/088 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L21/76801 ,  H01L27/088 ,  H01L29/4238

Abstract: A semiconductor integrated circuit device formed on the basis of the design rules of 0.5 .mu.m or less contains a MOS transistor. The MOS transistor is formed at the main surface region of the semiconductor substrate. If the effective gate area of the MOS transistor is S2 and the area of a contact hole made in an interlayer insulating film on the gate electrode of the MOS transistor is S1, the relationship expressed as S1/S2.ltoreq.1.8 is established. The contact hole is made by RIE techniques.

Abstract translation: 基于0.5μm或更小的设计规则形成的半导体集成电路器件包含MOS晶体管。 MOS晶体管形成在半导体衬底的主表面区域。 如果MOS晶体管的有效栅极面积为S2，并且在MOS晶体管的栅电极上的层间绝缘膜中形成的接触孔的面积为S1，则建立表示为S1 / S2的关系。 接触孔由RIE技术制成。

公开(公告)号：US5866938A

公开(公告)日：1999-02-02

申请号：US698349

申请日：1996-08-15

Applicant: Mariko Takagi ,  Ichiro Yoshii ,  Kaoru Hama ,  Naoki Ikeda ,  Hiroaki Yasuda

Inventor： Mariko Takagi ,  Ichiro Yoshii ,  Kaoru Hama ,  Naoki Ikeda ,  Hiroaki Yasuda

IPC: H01L21/82 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/525 ,  H01L29/43 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: A semi conductor device is provided having the following arrangement. A first electrode is formed on the major surface of a semiconductor substrate and comprises a first Al connection layer formed over the semiconductor substrate and a barrier metal layer provided on, and electrically connected to, the first Al connection layer and serving as a barrier against the Al. An insulating film is formed over the semiconductor substrate so as to cover the first electrode. An opening is formed in the insulating film so as to partially expose the first electrode. An antifuse film is formed in a manner to partially cover the insulating film and contact with the barrier metal layer of the first electrode with the opening therebetween. The antifuse film is formed of silicon nitride whose nitrogen/silicon atomic composition ratio ranges from 0.6 to 1.2. A second electrode is formed over the antifuse film and comprised of a barrier metal layer serving as a barrier against the Al.

Abstract translation: 提供具有以下布置的半导体器件。 第一电极形成在半导体衬底的主表面上，并且包括形成在半导体衬底上的第一Al连接层和设置在第一Al连接层上并电连接到第一Al连接层的阻挡金属层，并且用作阻挡 Al。 在半导体衬底上形成绝缘膜以覆盖第一电极。 在绝缘膜上形成开口以使第一电极局部露出。 以部分地覆盖绝缘膜并且与第一电极的阻挡金属层接触的方式形成反熔丝，其间具有开口。 反熔丝由氮/硅原子组成比为0.6〜1.2的氮化硅构成。 第二电极形成在反熔丝薄膜之上，并且包括用作阻挡Al的阻挡金属层。

公开(公告)号：US5550400A

公开(公告)日：1996-08-27

申请号：US270458

申请日：1994-07-05

Applicant: Mariko Takagi ,  Ichiro Yoshii ,  Kaoru Hama ,  Naoki Ikeda ,  Hiroaki Yasuda

Inventor： Mariko Takagi ,  Ichiro Yoshii ,  Kaoru Hama ,  Naoki Ikeda ,  Hiroaki Yasuda

IPC: H01L21/82 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/52 ,  H01L23/525 ,  H01L29/43 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002 ,  H01L2924/3011

Abstract: A semiconductor device is provided having the following arrangement. A first electrode is formed on the major surface of a semiconductor substrate and comprises a first Al connection layer formed over the semiconductor substrate and a barrier metal layer provided on, and electrically connected to, the first Al connection layer and serving as a barrier against the Al. An insulating film is formed over the semiconductor substrate so as to cover the first electrode. An opening is formed in the insulating film so as to partially expose the first electrode. An antifuse film is formed in a manner to partially cover the insulating film and contact with the barrier metal layer of the first electrode with the opening therebetween. The antifuse film is formed of silicon nitride whose nitrogen/silicon atomic composition ratio ranges from 0.6 to 1.2. A second electrode is formed over the antifuse film and comprised of a barrier metal layer serving as a barrier against the Al.

Abstract translation: 提供具有以下布置的半导体器件。 第一电极形成在半导体衬底的主表面上，并且包括形成在半导体衬底上的第一Al连接层和设置在第一Al连接层上并电连接到第一Al连接层的阻挡金属层，并且用作阻挡 Al。 在半导体衬底上形成绝缘膜以覆盖第一电极。 在绝缘膜上形成开口以使第一电极局部露出。 以部分地覆盖绝缘膜并且与第一电极的阻挡金属层接触的方式形成反熔丝，其间具有开口。 反熔丝由氮/硅原子组成比为0.6〜1.2的氮化硅构成。 第二电极形成在反熔丝薄膜之上，并且包括用作阻挡Al的阻挡金属层。