Spurious-free fractional-N frequency synthesizer with multi-phase network circuit
    1.
    发明授权
    Spurious-free fractional-N frequency synthesizer with multi-phase network circuit 有权
    具有多相网络电路的无杂散分数N频率合成器

    公开(公告)号:US06642800B2

    公开(公告)日:2003-11-04

    申请号:US10116555

    申请日:2002-04-04

    IPC分类号: H03L706

    摘要: A spurious-free fractional-N frequency synthesizer circuit is disclosed. The synthesizer circuit includes a multi-phase network circuit operative to provide output signals that are at least a 1/(2n+1)) fractional version of the input signal. The synthesizer circuit includes a phase lock loop (PLL) circuit, with the multi-phase network circuit being coupled to the negative feedback loop of the PLL. The multi-phase network circuit includes a smoothing circuit that removes any jitter present at the output of the PLL.

    摘要翻译: 公开了一种无杂散分数N频率合成器电路。 合成器电路包括多相网络电路,其操作以提供输入信号的至少1 /(2n + 1))分数版本的输出信号。 合成器电路包括锁相环(PLL)电路,多相网络电路耦合到PLL的负反馈环路。 多相网络电路包括一个平滑电路,其消除存在于PLL输出端的任何抖动。

    Low-Voltage Oscillator with Capacitor-Ratio Selectable Duty Cycle and Single-Input Sub-Threshold-Conducting Comparators to S-R Latch
    2.
    发明申请
    Low-Voltage Oscillator with Capacitor-Ratio Selectable Duty Cycle and Single-Input Sub-Threshold-Conducting Comparators to S-R Latch 有权
    具有电容比选择占空比的低电压振荡器和S-R锁存器的单输入子阈值导通比较器

    公开(公告)号:US20090146749A1

    公开(公告)日:2009-06-11

    申请号:US11952127

    申请日:2007-12-06

    IPC分类号: H03K3/26

    CPC分类号: H03K4/501

    摘要: An oscillator operates at a very low voltage yet has a duty cycle that is set by a ratio of capacitors that are charged and discharged. Sub-threshold p-channel transistors conduct sub-threshold currents below the normal threshold voltage, and drive set and reset inputs of a set-reset S-R latch. The S-R latch drives the oscillator outputs. The oscillator outputs feed back to charging p-channel transistors that charge one plate of the capacitors. During half of the cycle, the charging p-channel transistor is off, allowing one plate of the capacitors to discharge through an n-channel discharge transistor. After a period of discharge determined by the capacitance of the capacitor, the gate of a sub-threshold p-channel transistor falls enough for sub-threshold current to flow, triggering the set or reset input of the S-R latch. Since sub-threshold currents are needed to toggle the S-R latch, the oscillator begins to oscillate below the threshold voltage.

    摘要翻译: 振荡器在非常低的电压下工作,但是具有由充电和放电的电容器的比率设定的占空比。 子阈值p沟道晶体管导通低于正常阈值电压的次阈值电流,以及设置复位S-R锁存器的驱动器设置和复位输入。 S-R锁存器驱动振荡器输出。 振荡器输出反馈给对一个电容器板充电的p沟道晶体管。 在半周期中,充电p沟道晶体管截止,允许电容器的一个板通过n沟道放电晶体管放电。 在通过电容器的电容确定的放电周期之后,子阈值p沟道晶体管的栅极对于亚阈值电流流下来足以触发S-R锁存器的置位或复位输入。 由于需要次阈值电流来切换S-R锁存器,所以振荡器开始振荡低于阈值电压。