Low-Voltage Oscillator with Capacitor-Ratio Selectable Duty Cycle and Single-Input Sub-Threshold-Conducting Comparators to S-R Latch
    1.
    发明申请
    Low-Voltage Oscillator with Capacitor-Ratio Selectable Duty Cycle and Single-Input Sub-Threshold-Conducting Comparators to S-R Latch 有权
    具有电容比选择占空比的低电压振荡器和S-R锁存器的单输入子阈值导通比较器

    公开(公告)号:US20090146749A1

    公开(公告)日:2009-06-11

    申请号:US11952127

    申请日:2007-12-06

    IPC分类号: H03K3/26

    CPC分类号: H03K4/501

    摘要: An oscillator operates at a very low voltage yet has a duty cycle that is set by a ratio of capacitors that are charged and discharged. Sub-threshold p-channel transistors conduct sub-threshold currents below the normal threshold voltage, and drive set and reset inputs of a set-reset S-R latch. The S-R latch drives the oscillator outputs. The oscillator outputs feed back to charging p-channel transistors that charge one plate of the capacitors. During half of the cycle, the charging p-channel transistor is off, allowing one plate of the capacitors to discharge through an n-channel discharge transistor. After a period of discharge determined by the capacitance of the capacitor, the gate of a sub-threshold p-channel transistor falls enough for sub-threshold current to flow, triggering the set or reset input of the S-R latch. Since sub-threshold currents are needed to toggle the S-R latch, the oscillator begins to oscillate below the threshold voltage.

    摘要翻译: 振荡器在非常低的电压下工作,但是具有由充电和放电的电容器的比率设定的占空比。 子阈值p沟道晶体管导通低于正常阈值电压的次阈值电流,以及设置复位S-R锁存器的驱动器设置和复位输入。 S-R锁存器驱动振荡器输出。 振荡器输出反馈给对一个电容器板充电的p沟道晶体管。 在半周期中,充电p沟道晶体管截止,允许电容器的一个板通过n沟道放电晶体管放电。 在通过电容器的电容确定的放电周期之后,子阈值p沟道晶体管的栅极对于亚阈值电流流下来足以触发S-R锁存器的置位或复位输入。 由于需要次阈值电流来切换S-R锁存器,所以振荡器开始振荡低于阈值电压。

    Low voltage synchronous oscillator for DC-DC converter
    2.
    发明授权
    Low voltage synchronous oscillator for DC-DC converter 有权
    用于DC-DC转换器的低压同步振荡器

    公开(公告)号:US07656240B2

    公开(公告)日:2010-02-02

    申请号:US11869616

    申请日:2007-10-09

    IPC分类号: H03K3/03

    摘要: Systems and methods which provide an oscillator circuit outputting non-overlapping trigger signals throughout a range of operating voltages using a reset-set (RS) flip-flop type circuit configuration are shown. Embodiments utilize output driver buffers internal to the RS flip-flop circuit configuration to provide oscillator feedback delay. Feedback control circuitry may be implemented to ensure that the delay associated with any one driver buffer does not solely provide the feedback delay. Embodiments further implement input delay circuitry adapted to maintain a relatively constant reset and set input feedback delay ratio throughout a large range of operating conditions.

    摘要翻译: 示出了提供使用复位(RS)触发器型电路配置在整个工作电压范围内输出非重叠触发信号的振荡器电路的系统和方法。 实施例利用RS触发器电路配置内部的输出驱动器缓冲器来提供振荡器反馈延迟。 可以实现反馈控制电路以确保与任何一个驱动器缓冲器相关联的延迟不仅仅提供反馈延迟。 实施例进一步实现了输入延迟电路,其适于在整个操作条件的大范围内维持相对恒定的复位和设置输入反馈延迟比。

    Feedback controller having multiple feedback paths
    3.
    发明申请
    Feedback controller having multiple feedback paths 有权
    反馈控制器具有多个反馈路径

    公开(公告)号:US20080238396A1

    公开(公告)日:2008-10-02

    申请号:US11731167

    申请日:2007-03-30

    IPC分类号: G05F1/10 H03K5/153

    摘要: A feedback controller comprises first and second feedback circuits. The first feedback circuit is connected between an input node and an output node and has an error node. The first feedback circuit comprising a feedback amplifier for comparing a feedback signal to a reference signal and providing an error signal, and a comparator for comparing the error signal to a second reference signal and providing an output signal. The second feedback circuit is connected between the input node and the error node and comprises a current source coupled to the error node and a controller coupled to the input node for controlling the current source in response to a value of the feedback signal being above or below a threshold value.

    摘要翻译: 反馈控制器包括第一和第二反馈电路。 第一反馈电路连接在输入节点和输出节点之间,并具有错误节点。 第一反馈电路包括用于将反馈信号与参考信号进行比较并提供误差信号的反馈放大器,以及用于将误差信号与第二参考信号进行比较并提供输出信号的比较器。 所述第二反馈电路连接在所述输入节点和所述误差节点之间,并且包括耦合到所述误差节点的电流源和耦合到所述输入节点的控制器,用于响应于所述反馈信号的值高于或低于 一个阈值。

    Feedback controller having multiple feedback paths
    4.
    发明授权
    Feedback controller having multiple feedback paths 有权
    反馈控制器具有多个反馈路径

    公开(公告)号:US07948224B2

    公开(公告)日:2011-05-24

    申请号:US11731167

    申请日:2007-03-30

    IPC分类号: G05F1/00

    摘要: A feedback controller comprises first and second feedback circuits. The first feedback circuit is connected between an input node and an output node and has an error node. The first feedback circuit comprising a feedback amplifier for comparing a feedback signal to a reference signal and providing an error signal, and a comparator for comparing the error signal to a second reference signal and providing an output signal. The second feedback circuit is connected between the input node and the error node and comprises a current source coupled to the error node and a controller coupled to the input node for controlling the current source in response to a value of the feedback signal being above or below a threshold value.

    摘要翻译: 反馈控制器包括第一和第二反馈电路。 第一反馈电路连接在输入节点和输出节点之间,并具有错误节点。 第一反馈电路包括用于将反馈信号与参考信号进行比较并提供误差信号的反馈放大器,以及用于将误差信号与第二参考信号进行比较并提供输出信号的比较器。 所述第二反馈电路连接在所述输入节点和所述误差节点之间,并且包括耦合到所述误差节点的电流源和耦合到所述输入节点的控制器,用于响应于所述反馈信号的值在上方或下方来控制所述电流源 一个阈值。

    LOW VOLTAGE SYNCHRONOUS OSCILLATOR FOR DC-DC CONVERTER
    5.
    发明申请
    LOW VOLTAGE SYNCHRONOUS OSCILLATOR FOR DC-DC CONVERTER 有权
    用于DC-DC转换器的低电压同步振荡器

    公开(公告)号:US20090091399A1

    公开(公告)日:2009-04-09

    申请号:US11869616

    申请日:2007-10-09

    IPC分类号: H03K3/03

    摘要: Systems and methods which provide an oscillator circuit outputting non-overlapping trigger signals throughout a range of operating voltages using a reset-set (RS) flip-flop type circuit configuration are shown. Embodiments utilize output driver buffers internal to the RS flip-flop circuit configuration to provide oscillator feedback delay. Feedback control circuitry may be implemented to ensure that the delay associated with any one driver buffer does not solely provide the feedback delay. Embodiments further implement input delay circuitry adapted to maintain a relatively constant reset and set input feedback delay ratio throughout a large range of operating conditions.

    摘要翻译: 示出了提供使用复位(RS)触发器型电路配置在整个工作电压范围内输出非重叠触发信号的振荡器电路的系统和方法。 实施例利用RS触发器电路配置内部的输出驱动器缓冲器来提供振荡器反馈延迟。 可以实现反馈控制电路以确保与任何一个驱动器缓冲器相关联的延迟不仅仅提供反馈延迟。 实施例进一步实现了输入延迟电路,其适于在整个操作条件的大范围内维持相对恒定的复位和设置输入反馈延迟比。

    Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock
    6.
    发明申请
    Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock 有权
    使用电压升压时钟的单功率晶体管电池充电电路

    公开(公告)号:US20110267008A1

    公开(公告)日:2011-11-03

    申请号:US13179107

    申请日:2011-07-08

    IPC分类号: H02J7/00

    CPC分类号: H02J7/0031

    摘要: A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.

    摘要翻译: 充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。 单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。 门通过栅极耦合晶体管连接到充电器节点,以关闭功率晶体管,从而提供电池隔离。 门通过由使能信号激活的开关由升压时钟驱动。 使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。 比较器比较充电器和电池节点的电压,并且比较输出被锁存以产生使能信号。 反向使能信号激活第二开关,其将升压电压的时钟驱动到栅极耦合晶体管的栅极以截止功率晶体管。

    Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock
    7.
    发明申请
    Single-Power-Transistor Battery-Charging Circuit Using Voltage-Boosted Clock 有权
    使用电压升压时钟的单功率晶体管电池充电电路

    公开(公告)号:US20100148727A1

    公开(公告)日:2010-06-17

    申请号:US12336514

    申请日:2008-12-16

    IPC分类号: H02J7/00

    CPC分类号: H02J7/0031

    摘要: A charge/discharge protection circuit protects a battery from inadvertent shorting on a charger node that can connect to a charger or to a power supply of a portable electronic device. A single n-channel power transistor has a gate that controls a channel between the battery and the charger node. The gate is connected to the charger node by a gate-coupling transistor to turn off the power transistor, providing battery isolation. The gate is driven by a voltage-boosted clock through a switch activated by an enable signal. The enable signal also activates a grounding transistor to ground a gate of the gate-coupling transistor. A comparator compares voltages of the charger and battery nodes, and the compare output is latched to generate the enable signal. An inverse enable signal activates a second switch that drives the voltage-boosted clock to the gate of the gate-coupling transistor to turn off the power transistor.

    摘要翻译: 充电/放电保护电路可保护电池免受可连接到充电器或便携式电子设备的电源的充电器节点上的意外短路。 单个n沟道功率晶体管具有控制电池和充电器节点之间的通道的栅极。 门通过栅极耦合晶体管连接到充电器节点,以关闭功率晶体管,从而提供电池隔离。 门通过由使能信号激活的开关由升压时钟驱动。 使能信号还激活接地晶体管以对栅极耦合晶体管的栅极接地。 比较器比较充电器和电池节点的电压,并且比较输出被锁存以产生使能信号。 反向使能信号激活第二开关,其将升压电压的时钟驱动到栅极耦合晶体管的栅极,以关断功率晶体管。