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公开(公告)号：US20090045867A1
公开(公告)日：2009-02-19
申请号：US11838051
申请日：2007-08-13
IPC分类号： H01H85/00
摘要： The fuse cell architecture 371 for the presently claimed invention employs a multiple fuse structure 301, 302 architecture in lieu of a single fuse structure. As such, the terminals of these fuse structures that couple to other on-chip devices are always at ground potential throughout the application of programming voltage to the fuse pads 311. This approach overcomes previous single fuse problems owing to the fact that a sufficiently high programming voltage can be applied to blow fuse structures with unexpectedly high resistance without damaging nearby on-chip devices. Furthermore, even if one of the fuse structures 301, 302 possessed an abnormally high resistance which would not be blown under typical conditions, the desired circuit trimming result can still be achieved owing to the blowing of the other fuse structure in the fuse cell 371.
摘要翻译： 用于当前要求保护的发明的熔丝单元结构371采用多个熔丝结构301,302代替单个熔丝结构。 因此，耦合到其它片上器件的这些熔丝结构的端子在编程电压施加到熔丝焊盘311时始终处于地电位。由于以下事实，该方法克服了先前的单熔丝问题，这是因为足够高的编程 可以施加电压来熔断具有意想不到的高电阻的熔丝结构，而不会损坏附近的片上器件。 此外，即使保险丝结构301,302中的一个具有在典型条件下不会被烧断的异常高电阻，由于熔丝单元371中的另一熔丝结构的吹动，仍然可以实现期望的电路修整结果。
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公开(公告)号：US07659780B2
公开(公告)日：2010-02-09
申请号：US11947085
申请日：2007-11-29
申请人： Chit Ah Mak , Chun Fai Wong , Lap Chi Leung , Xiaofei Kuang , Jennifer Shuet Yan Ho , David Kwok Kuen Kwong
发明人： Chit Ah Mak , Chun Fai Wong , Lap Chi Leung , Xiaofei Kuang , Jennifer Shuet Yan Ho , David Kwok Kuen Kwong
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F1/3211 , H03F1/486 , H03F1/56 , H03F3/45192 , H03F2200/36 , H03F2200/513 , H03F2203/45138 , H03F2203/45356 , H03G1/0023 , H03G7/004 , H03G7/06
摘要： A gain control circuit including a resistor with a first terminal and a second terminal; an operational amplifier with an inverting terminal thereof electrically coupled to said first terminal of said resistor; a non-inverting terminal thereof; and an output terminal thereof; an amplifier circuit for transforming the voltage change of said operational amplifier output into a substantially exponential current change; wherein the output of said amplifier circuit is electrically coupled to said inverting terminal of said operational amplifier. The above described gain control circuit is able to perform wide bandwidth input signal buffering with linearity under low voltage and low power conditions. The circuit also offers low output impedances without the need of additional buffers and hence minimizing circuit size and manufacturing costs.
摘要翻译： 一种增益控制电路，包括具有第一端子和第二端子的电阻器; 运算放大器，其反相端电耦合到所述电阻器的所述第一端子; 其非反相端子; 及其输出端子; 放大器电路，用于将所述运算放大器输出的电压变化变换成基本指数的电流变化; 其中所述放大器电路的输出电耦合到所述运算放大器的所述反相端。 上述增益控制电路能够在低电压和低功率条件下以线性度执行宽带宽输入信号缓冲。 该电路还提供低输出阻抗，而不需要额外的缓冲器，因此最小化电路尺寸和制造成本。
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公开(公告)号：US20080238396A1
公开(公告)日：2008-10-02
申请号：US11731167
申请日：2007-03-30
申请人： Chik Wai Ng , Yat To Wong , David Kwok Kuen Kwong
发明人： Chik Wai Ng , Yat To Wong , David Kwok Kuen Kwong
CPC分类号： H03K7/08 , H03F3/217 , H03F3/45475
摘要： A feedback controller comprises first and second feedback circuits. The first feedback circuit is connected between an input node and an output node and has an error node. The first feedback circuit comprising a feedback amplifier for comparing a feedback signal to a reference signal and providing an error signal, and a comparator for comparing the error signal to a second reference signal and providing an output signal. The second feedback circuit is connected between the input node and the error node and comprises a current source coupled to the error node and a controller coupled to the input node for controlling the current source in response to a value of the feedback signal being above or below a threshold value.
摘要翻译： 反馈控制器包括第一和第二反馈电路。 第一反馈电路连接在输入节点和输出节点之间，并具有错误节点。 第一反馈电路包括用于将反馈信号与参考信号进行比较并提供误差信号的反馈放大器，以及用于将误差信号与第二参考信号进行比较并提供输出信号的比较器。 所述第二反馈电路连接在所述输入节点和所述误差节点之间，并且包括耦合到所述误差节点的电流源和耦合到所述输入节点的控制器，用于响应于所述反馈信号的值高于或低于 一个阈值。
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公开(公告)号：US07948224B2
公开(公告)日：2011-05-24
申请号：US11731167
申请日：2007-03-30
申请人： Chik Wai Ng , Yat To Wong , David Kwok Kuen Kwong
发明人： Chik Wai Ng , Yat To Wong , David Kwok Kuen Kwong
IPC分类号： G05F1/00
CPC分类号： H03K7/08 , H03F3/217 , H03F3/45475
摘要： A feedback controller comprises first and second feedback circuits. The first feedback circuit is connected between an input node and an output node and has an error node. The first feedback circuit comprising a feedback amplifier for comparing a feedback signal to a reference signal and providing an error signal, and a comparator for comparing the error signal to a second reference signal and providing an output signal. The second feedback circuit is connected between the input node and the error node and comprises a current source coupled to the error node and a controller coupled to the input node for controlling the current source in response to a value of the feedback signal being above or below a threshold value.
摘要翻译： 反馈控制器包括第一和第二反馈电路。 第一反馈电路连接在输入节点和输出节点之间，并具有错误节点。 第一反馈电路包括用于将反馈信号与参考信号进行比较并提供误差信号的反馈放大器，以及用于将误差信号与第二参考信号进行比较并提供输出信号的比较器。 所述第二反馈电路连接在所述输入节点和所述误差节点之间，并且包括耦合到所述误差节点的电流源和耦合到所述输入节点的控制器，用于响应于所述反馈信号的值在上方或下方来控制所述电流源 一个阈值。
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5.发明申请Low-Voltage Oscillator with Capacitor-Ratio Selectable Duty Cycle and Single-Input Sub-Threshold-Conducting Comparators to S-R Latch 有权具有电容比选择占空比的低电压振荡器和S-R锁存器的单输入子阈值导通比较器公开(公告)号：US20090146749A1
公开(公告)日：2009-06-11
申请号：US11952127
申请日：2007-12-06
申请人： Chik Wai Ng , Yat To Wong , Ho Ming Wan , David Kwok Kuen Kwong
发明人： Chik Wai Ng , Yat To Wong , Ho Ming Wan , David Kwok Kuen Kwong
IPC分类号： H03K3/26
CPC分类号： H03K4/501
摘要： An oscillator operates at a very low voltage yet has a duty cycle that is set by a ratio of capacitors that are charged and discharged. Sub-threshold p-channel transistors conduct sub-threshold currents below the normal threshold voltage, and drive set and reset inputs of a set-reset S-R latch. The S-R latch drives the oscillator outputs. The oscillator outputs feed back to charging p-channel transistors that charge one plate of the capacitors. During half of the cycle, the charging p-channel transistor is off, allowing one plate of the capacitors to discharge through an n-channel discharge transistor. After a period of discharge determined by the capacitance of the capacitor, the gate of a sub-threshold p-channel transistor falls enough for sub-threshold current to flow, triggering the set or reset input of the S-R latch. Since sub-threshold currents are needed to toggle the S-R latch, the oscillator begins to oscillate below the threshold voltage.
摘要翻译： 振荡器在非常低的电压下工作，但是具有由充电和放电的电容器的比率设定的占空比。 子阈值p沟道晶体管导通低于正常阈值电压的次阈值电流，以及设置复位S-R锁存器的驱动器设置和复位输入。 S-R锁存器驱动振荡器输出。 振荡器输出反馈给对一个电容器板充电的p沟道晶体管。 在半周期中，充电p沟道晶体管截止，允许电容器的一个板通过n沟道放电晶体管放电。 在通过电容器的电容确定的放电周期之后，子阈值p沟道晶体管的栅极对于亚阈值电流流下来足以触发S-R锁存器的置位或复位输入。 由于需要次阈值电流来切换S-R锁存器，所以振荡器开始振荡低于阈值电压。
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公开(公告)号：US20090140808A1
公开(公告)日：2009-06-04
申请号：US11947085
申请日：2007-11-29
申请人： Chit Ah MAK , Chun Fai WONG , Lap Chi LEUNG , Xiaofei KUANG , Jennifer Shuet Yan HO , David Kwok Kuen KWONG
发明人： Chit Ah MAK , Chun Fai WONG , Lap Chi LEUNG , Xiaofei KUANG , Jennifer Shuet Yan HO , David Kwok Kuen KWONG
IPC分类号： H03F3/45
CPC分类号： H03F3/45475 , H03F1/3211 , H03F1/486 , H03F1/56 , H03F3/45192 , H03F2200/36 , H03F2200/513 , H03F2203/45138 , H03F2203/45356 , H03G1/0023 , H03G7/004 , H03G7/06
摘要： A gain control circuit including a resistor with a first terminal and a second terminal; an operational amplifier with an inverting terminal thereof electrically coupled to said first terminal of said resistor; a non-inverting terminal thereof; and an output terminal thereof; an amplifier circuit for transforming the voltage change of said operational amplifier output into a substantially exponential current change; wherein the output of said amplifier circuit is electrically coupled to said inverting terminal of said operational amplifier. The above described gain control circuit is able to perform wide bandwidth input signal buffering with linearity under low voltage and low power conditions. The circuit also offers low output impedances without the need of additional buffers and hence minimizing circuit size and manufacturing costs.
摘要翻译： 一种增益控制电路，包括具有第一端子和第二端子的电阻器; 运算放大器，其反相端电耦合到所述电阻器的所述第一端子; 其非反相端子; 及其输出端子; 放大器电路，用于将所述运算放大器输出的电压变化变换成基本指数的电流变化; 其中所述放大器电路的输出电耦合到所述运算放大器的所述反相端。 上述增益控制电路能够在低电压和低功率条件下以线性方式执行宽带宽输入信号缓冲。 该电路还提供低输出阻抗，而不需要额外的缓冲器，因此最小化电路尺寸和制造成本。
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公开(公告)号：US20090091399A1
公开(公告)日：2009-04-09
申请号：US11869616
申请日：2007-10-09
IPC分类号： H03K3/03
CPC分类号： H03K5/1515 , H03K3/017 , H03K5/133
摘要： Systems and methods which provide an oscillator circuit outputting non-overlapping trigger signals throughout a range of operating voltages using a reset-set (RS) flip-flop type circuit configuration are shown. Embodiments utilize output driver buffers internal to the RS flip-flop circuit configuration to provide oscillator feedback delay. Feedback control circuitry may be implemented to ensure that the delay associated with any one driver buffer does not solely provide the feedback delay. Embodiments further implement input delay circuitry adapted to maintain a relatively constant reset and set input feedback delay ratio throughout a large range of operating conditions.
摘要翻译： 示出了提供使用复位（RS）触发器型电路配置在整个工作电压范围内输出非重叠触发信号的振荡器电路的系统和方法。 实施例利用RS触发器电路配置内部的输出驱动器缓冲器来提供振荡器反馈延迟。 可以实现反馈控制电路以确保与任何一个驱动器缓冲器相关联的延迟不仅仅提供反馈延迟。 实施例进一步实现了输入延迟电路，其适于在整个操作条件的大范围内维持相对恒定的复位和设置输入反馈延迟比。
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公开(公告)号：US07656240B2
公开(公告)日：2010-02-02
申请号：US11869616
申请日：2007-10-09
IPC分类号： H03K3/03
CPC分类号： H03K5/1515 , H03K3/017 , H03K5/133
摘要： Systems and methods which provide an oscillator circuit outputting non-overlapping trigger signals throughout a range of operating voltages using a reset-set (RS) flip-flop type circuit configuration are shown. Embodiments utilize output driver buffers internal to the RS flip-flop circuit configuration to provide oscillator feedback delay. Feedback control circuitry may be implemented to ensure that the delay associated with any one driver buffer does not solely provide the feedback delay. Embodiments further implement input delay circuitry adapted to maintain a relatively constant reset and set input feedback delay ratio throughout a large range of operating conditions.
摘要翻译： 示出了提供使用复位（RS）触发器型电路配置在整个工作电压范围内输出非重叠触发信号的振荡器电路的系统和方法。 实施例利用RS触发器电路配置内部的输出驱动器缓冲器来提供振荡器反馈延迟。 可以实现反馈控制电路以确保与任何一个驱动器缓冲器相关联的延迟不仅仅提供反馈延迟。 实施例进一步实现了输入延迟电路，其适于在整个操作条件的大范围内维持相对恒定的复位和设置输入反馈延迟比。
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公开(公告)号：US07538597B2
公开(公告)日：2009-05-26
申请号：US11838051
申请日：2007-08-13
IPC分类号： H03H37/76
摘要： The fuse cell architecture 371 for the presently claimed invention employs a multiple fuse structure 301, 302 architecture in lieu of a single fuse structure. As such, the terminals of these fuse structures that couple to other on-chip devices are always at ground potential throughout the application of programming voltage to the fuse pads 311. This approach overcomes previous single fuse problems owing to the fact that a sufficiently high programming voltage can be applied to blow fuse structures with unexpectedly high resistance without damaging nearby on-chip devices. Furthermore, even if one of the fuse structures 301, 302 possessed an abnormally high resistance which would not be blown under typical conditions, the desired circuit trimming result can still be achieved owing to the blowing of the other fuse structure in the fuse cell 371.
摘要翻译： 用于当前要求保护的发明的熔丝单元结构371采用多个熔丝结构301,302代替单个熔丝结构。 因此，耦合到其它片上器件的这些熔丝结构的端子在编程电压施加到熔丝焊盘311时始终处于地电位。由于以下事实，该方法克服了先前的单熔丝问题，这是因为足够高的编程 可以施加电压来熔断具有意想不到的高电阻的熔丝结构，而不会损坏附近的片上器件。 此外，即使保险丝结构301,302中的一个具有在典型条件下不会被烧断的异常高电阻，由于熔丝单元371中的另一熔丝结构的吹动，仍然可以实现期望的电路修整结果。
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