公开(公告)号：US06778170B1

公开(公告)日：2004-08-17

申请号：US09666666

申请日：2000-04-07

Applicant: Hongjun Shu ,  Osamu Kobayashi ,  Wen-jyh Wang

Inventor： Hongjun Shu ,  Osamu Kobayashi ,  Wen-jyh Wang

IPC: G09G500

CPC classification number: G09G5/003 ,  G09G2310/08

Abstract: Displaying the images encoded in a display signal which also contains synchronization signals and display enable (DE) signal. The DE signal indicates the time points at which the display data portion of the display signal contains active pixel data elements representing image frames. A display unit generates HDISP and VDISP signals (indicative of the active time in which active pixels and lines are respectively received) based on the DE signal. As the DE signal generally tracks (in the time domain) the active pixel data elements, the active pixel data elements forming image frames are accurately identified, and a superior image quality generally results.

Abstract translation: 显示以包含同步信号和显示使能（DE）信号的显示信号编码的图像。 DE信号指示显示信号的显示数据部分包含表示图像帧的有源像素数据元素的时间点。 显示单元基于DE信号生成HDISP和VDISP信号（指示分别接收有源像素和线的有效时间）。 由于DE信号通常跟踪（在时域中）有源像素数据元素，所以准确地识别形成图像帧的有源像素数据元素，并且通常导致优异的图像质量。

公开(公告)号：US5831640A

公开(公告)日：1998-11-03

申请号：US770453

申请日：1996-12-20

Applicant: Vincent W. Wang ,  Jih-Hsien Soong ,  Hongjun Shu ,  Tzoyao Chan

Inventor： Vincent W. Wang ,  Jih-Hsien Soong ,  Hongjun Shu ,  Tzoyao Chan

IPC: G06T1/20 ,  G06F12/08 ,  G06T1/60 ,  G06T15/04 ,  G06T15/10 ,  G06F13/16

CPC classification number: G06F12/0875 ,  G06T15/04 ,  G06T15/10

Abstract: A circuit and method for increasing the processing efficiency of texture map data requests within a 3D subunit of a computer controlled graphics display system. The 3D graphics display subsystem includes a polygon engine, a texture map engine and a pixel pipeline. The texture map engine contains a texture map data access (TDA) circuit having a cache controller with a computer readable cache memory for containing recently used texture maps stored in (u,v) coordinate space. The cache controller is limited in handling only n cache miss operations simultaneously. In one embodiment, n is 1. The TDA circuit also contains a texture map address (TMA) FIFO memory unit for storing texture map addresses associated with texture data requests that hit or missed in the cache memory unit. Since the cache controller handles up to n misses, the texture engine stalls when the (n+1).sup.th unprocessed texture request miss is encountered. Therefore, the TMA FIFO at any time contains at most n miss addresses therein. Processing efficiency is increased when a miss is encountered but the TMA FIFO contains unprocessed hit addresses. At this time, simultaneously with the cache controller fetching the texture data for the missed address, it can also advantageously: (1) supply data from the cache memory for the previously encountered and stored hit addresses; and (2) accept new hit addresses into the TMA FIFO thereby effectively avoiding a texture engine stall. This is quite unlike the prior art systems which process no hit addresses upon a texture miss but rather stall the texture engine.

Abstract translation: 一种用于增加计算机控制的图形显示系统的3D子单元内的纹理映射数据请求的处理效率的电路和方法。 3D图形显示子系统包括多边形引擎，纹理映射引擎和像素管道。 纹理映射引擎包含具有高速缓存控制器的纹理映射数据访问（TDA）电路，该缓存控制器具有计算机可读高速缓冲存储器，用于存储存储在（u，v）坐标空间中的最近使用的纹理映射。 缓存控制器在仅处理n个缓存未命中操作的同时受到限制。 在一个实施例中，n为1.TDA电路还包含纹理映射地址（TMA）FIFO存储器单元，用于存储与高速缓冲存储器单元中的命中或错过的纹理数据请求相关联的纹理映射地址。 由于缓存控制器处理多达n个未命中，当遇到第（n + 1）个未处理的纹理请求未命中时，纹理引擎停止。 因此，TMA FIFO在任何时候最多包含n个未命中的地址。 当遇到错过但是TMA FIFO包含未处理的命中地址时，处理效率会提高。 此时，与缓存控制器同时获取遗漏地址的纹理数据，还可以有利地：（1）从高速缓冲存储器提供先前遇到和存储的命中地址的数据; 和（2）接受新的命中地址到TMA FIFO，从而有效地避免纹理引擎失速。 这与现有技术的系统完全不同，这种系统在纹理丢失时不处理命中地址，而是阻止纹理引擎。