公开(公告)号：US07006931B2

公开(公告)日：2006-02-28

申请号：US10776716

申请日：2004-02-11

申请人： Alina Deutsch ,  Peter Feldmann ,  Albert E. Ruehli ,  Howard Harold Smith

发明人： Alina Deutsch ,  Peter Feldmann ,  Albert E. Ruehli ,  Howard Harold Smith

IPC分类号： G01R15/00

CPC分类号： G01R31/2813

摘要： A system and method for analyzing a circuit with transmission lines includes determining which sources influence each of a plurality of transmission lines, based on coupling factors. Transmission line parameters are computed based on the sources, which influence each transmission line. A transient response or frequency response is analyzed for each transmission line by segmenting each line to perform an analysis on that line. The step of analyzing is repeated using waveforms determined in a previous iteration until convergence to a resultant waveform has occurred.

摘要翻译： 用于利用传输线分析电路的系统和方法包括基于耦合因素来确定哪些源影响多条传输线中的每一条。 传输线参数是基于影响每条传输线的源计算的。 通过分割每行来对每条传输线分析瞬态响应或频率响应，以对该行进行分析。 使用在先前迭代中确定的波形重复分析步骤，直到已经发生收敛到合成波形。

公开(公告)号：US06342823B1

公开(公告)日：2002-01-29

申请号：US09140643

申请日：1998-08-26

申请人： Allan Harvey Dansky ,  Alina Deutsch ,  Gerard Vincent Kopcsay ,  Phillip John Restle ,  Howard Harold Smith

发明人： Allan Harvey Dansky ,  Alina Deutsch ,  Gerard Vincent Kopcsay ,  Phillip John Restle ,  Howard Harold Smith

IPC分类号： H01P500

CPC分类号： G06F17/5036

摘要： A method and system for reducing the computation complexity and improving accuracy of delay and crosstalk calculation in transmission-lines with frequency-dependent losses. An analysis tool based on restricted coupled-line topologies, simple two-dimensional to three-dimensional RLC matrix conversion, and use of prestored synthesized circuits that accurately capture frequency-dependent loss effects. The CAD tool can handle frequency-dependent resistive and inductive effects for coupled-interconnections on large microprocessor chips with >10K of critical nets. This is done in an interactive manner during the design cycle and allows first path fast product design.

摘要翻译： 一种降低计算复杂度，提高频率依赖损耗的传输线延迟和串扰计算精度的方法和系统。 基于限制耦合线拓扑的分析工具，简单的二维至三维RLC矩阵转换，以及使用准备捕获频率相关损耗效应的预存储合成电路。 CAD工具可以处理具有> 10K关键网络的大型微处理器芯片上的耦合互连的频率相关电阻和电感效应。 这在设计周期中以交互的方式完成，并允许第一路径快速产品设计。

公开(公告)号：US6028989A

公开(公告)日：2000-02-22

申请号：US059220

申请日：1998-04-13

申请人： Allan Harvey Dansky ,  Howard Harold Smith ,  Fadi Yusuf Busaba ,  Michael Alexander Bowen ,  Adrian Zuckerman

发明人： Allan Harvey Dansky ,  Howard Harold Smith ,  Fadi Yusuf Busaba ,  Michael Alexander Bowen ,  Adrian Zuckerman

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5036

摘要： A program method for noise calculation and modeling caculates crosstalk voltage for a planned chip design, by first running routing and crosstalk routines for creating crosstalk rules for the planned design of a chip and loading crosstalk rules after routing is completed, and calculating the noise voltage of the planned design based on the exact topologies/paths of the victim and perpetrator nets of the planned design by path tracing and outputing a program file which contains the calculated noise voltage and a complete tabulation of the key physical and electrical parameters of the victim and perpetrator nets of the planned design, and then modeling using a network analysis program to selected nets of the design which exceed allowed noise limitations and obtaining the planned design net's network topology as an output while using the program file containing noise voltage calculation results as an input to the net's topology circuit simulation modeling program and outputting a nodal voltages vs. time data at each receiver location on a victim net as well as key nodes on any perpetrator nets of said planned design.

摘要翻译： 用于噪声计算和建模的程序方法通过首先运行路由和串扰例程来产生计划的芯片设计的串扰电压，以便在路由完成之后为芯片的计划设计设计串扰规则并加载串扰规则，并计算噪声电压 基于确定的受害者的拓扑/路径和计划设计的犯罪网络的计划设计，通过路径跟踪并输出包含计算的噪声电压的程序文件，以及完整列出受害者和肇事者的主要物理和电气参数 网络的计划设计，然后使用网络分析程序对设计的选定网络进行建模，超过允许的噪声限制，并将计划设计网络的网络拓扑结构作为输出，同时使用包含噪声电压计算结果的程序文件作为输入 网络拓扑电路仿真建模程序并输出节点 在受害者网络上的每个接收者位置处的时间数据与时间数据以及所述计划设计的任何犯罪网络上的关键节点。

公开(公告)号：US06279142B1

公开(公告)日：2001-08-21

申请号：US09165956

申请日：1998-10-02

申请人： Michael Alexander Bowen ,  Moises Cases ,  Howard Harold Smith

发明人： Michael Alexander Bowen ,  Moises Cases ,  Howard Harold Smith

IPC分类号： G06F1750

CPC分类号： G06F17/5077 ,  G06F17/5036

摘要： A method of on-chip interconnect design in an integrated circuit (IC) is provided. Fast circuit simulations of each net constituting the IC are performed for noise margin and slew rate analysis. A resistor/capacitor (RC) network for each net is generated from net lengths, and assignments of parasitic cross-coupling capacitances and shunt capacitances derived from three-dimensional field solver evaluations of pre-routing phase estimated wire geometries. If the noise margin and slew rate criteria are not satisfied for the net under simulation, the simulations are iterated, with a new wire geometry selected between iterations, until the criteria are satisfied. Each net is tagged with a wire geometry that satisfies noise margin and slew rate requirements which can then be passed to a routing tool.

摘要翻译： 提供了集成电路（IC）中片上互连设计的方法。 执行构成IC的每个网络的快速电路仿真，用于噪声容限和压摆率分析。 每个网络的电阻/电容（RC）网络由净长度产生，并且由预路由相位估计的线几何的三维场求解器评估得到的寄生交叉耦合电容和分流电容的分配。 如果模拟网络的噪声容限和转换速率标准不满足，则迭代模拟，在迭代之间选择新的线形几何，直到满足标准。 每个网络都标有线条几何，可满足噪声容限和压摆率要求，然后可将其传递给路由工具。