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公开(公告)号：US07006931B2
公开(公告)日：2006-02-28
申请号：US10776716
申请日：2004-02-11
IPC分类号： G01R15/00
CPC分类号： G01R31/2813
摘要： A system and method for analyzing a circuit with transmission lines includes determining which sources influence each of a plurality of transmission lines, based on coupling factors. Transmission line parameters are computed based on the sources, which influence each transmission line. A transient response or frequency response is analyzed for each transmission line by segmenting each line to perform an analysis on that line. The step of analyzing is repeated using waveforms determined in a previous iteration until convergence to a resultant waveform has occurred.
摘要翻译： 用于利用传输线分析电路的系统和方法包括基于耦合因素来确定哪些源影响多条传输线中的每一条。 传输线参数是基于影响每条传输线的源计算的。 通过分割每行来对每条传输线分析瞬态响应或频率响应，以对该行进行分析。 使用在先前迭代中确定的波形重复分析步骤，直到已经发生收敛到合成波形。
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公开(公告)号：US20050177325A1
公开(公告)日：2005-08-11
申请号：US10776716
申请日：2004-02-11
申请人： Alina Deutsch , Peter Feldmann , Albert Ruehli , Howard Smith
发明人： Alina Deutsch , Peter Feldmann , Albert Ruehli , Howard Smith
CPC分类号： G01R31/2813
摘要： A system and method for analyzing a circuit with transmission lines includes determining which sources influence each of a plurality of transmission lines, based on coupling factors. Transmission line parameters are computed based on the sources, which influence each transmission line. A transient response or frequency response is analyzed for each transmission line by segmenting each line to perform an analysis on that line. The step of analyzing is repeated using waveforms determined in a previous iteration until convergence to a resultant waveform has occurred.
摘要翻译： 用于使用传输线分析电路的系统和方法包括基于耦合因素来确定哪些源影响多条传输线中的每一条。 传输线参数是基于影响每条传输线的源计算的。 通过分割每行来对每条传输线分析瞬态响应或频率响应，以对该行进行分析。 使用在先前迭代中确定的波形重复分析步骤，直到已经发生收敛到合成波形。
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公开(公告)号：US08463571B2
公开(公告)日：2013-06-11
申请号：US12944892
申请日：2010-11-12
CPC分类号： G06F17/5036
摘要： A computer-implemented system, method, and storage device simulate a periodic voltage waveform in a network model of the integrated circuit design. The method then determines resultant current values in each segment of nets of the integrated circuit design resulting from the periodic voltage waveform and performs a Fourier transform of the periodic voltage waveform to generate a frequency domain representation of the periodic voltage waveform. The frequency domain representation comprises multiple Fourier terms, each of the Fourier terms is a frequency that is a multiple of the base frequency. Next, the method performs an AC analysis of the resultant voltage at each frequency of the multiple Fourier terms. The AC analysis provides an electrical current value for each of the frequencies of the Fourier terms for each of the nets. This allows the method to compute a root mean square current through each of the nets based on the AC analysis. Then, the method determines whether the root mean square current for any of the segments of the nets exceeds a current limit, and reports any segment of the nets for which the root mean square current exceeds the current limit.
摘要翻译： 计算机实现的系统，方法和存储设备模拟集成电路设计的网络模型中的周期性电压波形。 然后，该方法确定由周期性电压波形产生的集成电路设计的网络的每个段中的合成电流值，并执行周期性电压波形的傅立叶变换以产生周期性电压波形的频域表示。 频域表示包括多个傅立叶项，每个傅立叶项是基频的倍数的频率。 接下来，该方法对多傅里叶项的每个频率进行所得到的电压的AC分析。 AC分析为每个网络的傅立叶项的每个频率提供电流值。 这允许该方法基于AC分析来计算通过每个网络的均方根电流。 然后，该方法确定网络的任何段的均方根电流是否超过电流限制，并且报告均方根电流超过电流极限的网络的任何段。
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4.发明授权公开(公告)号：US08020129B2
公开(公告)日：2011-09-13
申请号：US12021723
申请日：2008-01-29
申请人： Soroush Abbaspour , Peter Feldmann
发明人： Soroush Abbaspour , Peter Feldmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.
摘要翻译： 描述了用于对数字集成电路执行多个电压阈值时序分析的方法。 在一个实施例中，存在多电压阈值时序分析工具，用于执行具有由互连电路加载的至少一个逻辑门的数字集成电路的多电压阈值时序分析。 在该实施例中，表征数据检索部件被配置为获得描述所述至少一个逻辑门的驱动行为的表征数据。 互连电路模型检索部件被配置为获得互连电路的模型。 多电压阈值时序分析部件被配置为导出驱动点电压波形的交叉时间序列以在连续的电压阈值之间前进。 多电压阈值时序分析部件还根据导出的交叉时间序列产生电压波形。
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5.发明授权Method, apparatus and computer program providing broadband preconditioning based on reduced coupling for numerical solvers 失效方法，装置和计算机程序提供基于减数耦合的数值求解器的宽带预处理公开(公告)号：US07933751B2
公开(公告)日：2011-04-26
申请号：US12192459
申请日：2008-08-15
申请人： Peter Feldmann , Jason D. Morsey , Barry J. Rubin
发明人： Peter Feldmann , Jason D. Morsey , Barry J. Rubin
CPC分类号： G06F17/12
摘要： This invention relates to computing numerical solutions of linear systems of equations, specifically to implementing preconditioning of the coefficient matrix of such a system. The preconditioning applies to any coefficient matrix, dense or sparse, based on the solutions of a physical problem of unknown functions, commonly referred to as basis or interpolation functions, where the basis function spans more then one mesh element. Examples of such linear systems can result from, as examples, an electromagnetic analysis of printed circuit boards or field scattering in radar applications, fluid mechanics and acoustics. A method and system to compute a preconditioner for a coefficient matrix A that is compatible with the linear system of equations that provides basis function support over at least two mesh elements. Coupling of the preconditioner between partitions of a portioned mesh representation is only through basis functions at the partition boundaries.
摘要翻译： 本发明涉及计算线性方程组的数值解，具体涉及实现这种系统的系数矩阵的预处理。 基于未知函数的物理问题的解决方案，通常称为基础函数或插值函数，其中基函数跨越多于一个网格元素，该预处理适用于任何密集或稀疏的系数矩阵。 作为示例，这种线性系统的示例可以从印刷电路板的电磁分析或雷达应用中的场散射，流体力学和声学等方面得到。 一种用于计算系数矩阵A的预处理器的方法和系统，该系数矩阵A与在至少两个网格元素上提供基函数支持的线性方程组兼容。 分段网格表示的分区之间的预处理器的耦合仅通过分区边界处的基函数。
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6.发明授权Method of modeling and employing the CMOS gate slew and output load dependent pin capacitance during timing analysis 失效在定时分析期间建模和采用CMOS栅极的方法和输出负载相关的引脚电容公开(公告)号：US07788617B2
公开(公告)日：2010-08-31
申请号：US12043455
申请日：2008-03-06
申请人： Adil Bhanji , Soroush Abbaspour , Peter Feldmann , Debjit Sinha
发明人： Adil Bhanji , Soroush Abbaspour , Peter Feldmann , Debjit Sinha
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An accurate method to compute the capacitance at a pin whose capacitance is slew dependant. The method uses existing library characterized data and provides an equation based approach which can easily be integrated in static timing analysis without the added resource needs that an iterative approach would require. An RC/RLC network from slew and output load dependent pin capacitance tables is generated. The resulting linear network which models the pin capacitance is then stitched to the original interconnect network and used to calculate the propagation delay across a gate and corresponding interconnect. The method steps include: a) determining a response of the gate pin capacitance to its input slew and output load; b) synthesizing a linear time-invariant filter that matches the response; c) extending the interconnect model to include the synthesized time-invariant filter; and d) inputting the extended interconnect model into a static timing analysis for determining timing behavior between a gate input and each of its fan-out gates.
摘要翻译： 一种精确的方法来计算电容与电容相关的引脚上的电容。 该方法使用现有的库特征数据，并提供了一种基于方程的方法，可以轻松地将其集成到静态时序分析中，而不需要迭代方法所需的附加资源。 产生来自压摆和输出负载的针电容表的RC / RLC网络。 所产生的对引脚电容进行建模的线性网络然后被缝合到原始互连网络，并用于计算跨栅极和相应互连的传播延迟。 方法步骤包括：a）确定栅极引脚电容对其输入转换和输出负载的响应; b）合成与响应匹配的线性时不变滤波器; c）扩展互连模型以包括合成的时不变滤波器; 以及d）将所述扩展互连模型输入到静态时序分析中，以确定门输入和每个扇出门之间的时序特性。
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7.发明申请公开(公告)号：US20090193373A1
公开(公告)日：2009-07-30
申请号：US12021723
申请日：2008-01-29
申请人： Soroush Abbaspour , Peter Feldmann
发明人： Soroush Abbaspour , Peter Feldmann
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： An approach for performing multiple voltage threshold timing analysis for a digital integrated circuit is described. In one embodiment, there is a multiple voltage threshold timing analysis tool for performing a multiple voltage threshold timing analysis of a digital integrated circuit having at least one logic gate loaded by an interconnect circuit. In this embodiment, a characterization data retrieving component is configured to obtain characterization data describing driving behavior of the at least one logic gate. An interconnect circuit model retrieving component is configured to obtain a model of the interconnect circuit. A multiple voltage threshold timing analysis component is configured to derive a sequence of crossing times for the driving point voltage waveform to advance between successive voltage thresholds. The multiple voltage threshold timing analysis component also generates a voltage waveform from the derived sequence of crossing times.
摘要翻译： 描述了用于对数字集成电路执行多个电压阈值时序分析的方法。 在一个实施例中，存在多电压阈值时序分析工具，用于执行具有由互连电路加载的至少一个逻辑门的数字集成电路的多电压阈值时序分析。 在该实施例中，表征数据检索部件被配置为获得描述所述至少一个逻辑门的驱动行为的表征数据。 互连电路模型检索部件被配置为获得互连电路的模型。 多电压阈值时序分析部件被配置为导出驱动点电压波形的交叉时间序列以在连续的电压阈值之间前进。 多电压阈值时序分析部件还根据导出的交叉时间序列产生电压波形。
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8.发明申请System and method for efficient model order reduction in electric and electronic circuit design 审中-公开电气和电子电路设计中有效降低模型顺序的系统和方法公开(公告)号：US20060080068A1
公开(公告)日：2006-04-13
申请号：US10961365
申请日：2004-10-07
申请人： Peter Feldmann , Ying Liu
发明人： Peter Feldmann , Ying Liu
IPC分类号： G06F17/10
CPC分类号： G06F17/504
摘要： The present invention comprises a system and method for reducing the order of models used to simulate complex electric circuits and linear systems. In particular, the method of the present invention comprises formulating expressions relating the input and output terminals of a complex electric circuit, wherein the expressions comprise a first model of the electric circuit; performing mathematical operations on the first model to reveal correlations between at least two input terminals or between at least two output terminals; and substituting a reduced order second model for the original first model, whereby the reduced order second model eliminates some or all aspects of correlations between input terminals or between output terminals. The system of the present invention comprises a computer system for performing model order reduction.
摘要翻译： 本发明包括一种用于减少用于模拟复杂电路和线性系统的模型的顺序的系统和方法。 特别地，本发明的方法包括制定与复合电路的输入和输出端相关的表达式，其中表达式包括电路的第一模型; 对所述第一模型执行数学运算以揭示至少两个输入端之间或至少两个输出端之间的相关性; 并且将所述原始第一模型代入减序二次模型，由此所述缩减顺序第二模型消除了输入端之间或输出端之间的相关的一些或所有方面。 本发明的系统包括用于执行模型订单减少的计算机系统。
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9.发明授权Method of making an integrated circuit including noise modeling and prediction 失效制造包括噪声建模和预测的集成电路的方法
公开(公告)号：US6072947A
公开(公告)日：2000-06-06
申请号：US933733
申请日：1997-09-23
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： A frequency-domain analysis method computes noise power spectral densities (PSDs) in nonlinear circuits. The method uses harmonic components of the periodic time-varying PSD of cyclostationary noise, i.e., harmonic power spectral densities which are deterministic functions that describe the time-varying second-order statistics of cyclostationary noise. A block-structured matrix equation is used which relates output noise statistics to input noise statistics. By exploiting Toeplitz block structure, an efficient noise calculation method requires O(nN log N) computation time and O(nN) memory, where n is the circuit size and N is the number of significant harmonics in the circuit's steady state. The method successfully treats device noise sources with arbitrarily shaped PSDs (including thermal, shot, and flicker noises), handles noise input correlations and computes correlations between different outputs.
摘要翻译： 频域分析方法计算非线性电路中的噪声功率谱密度（PSD）。 该方法使用循环平稳噪声的周期性时变PSD的谐波分量，即谐波功率谱密度，其是描述周期平稳噪声的时变二阶统计的确定性函数。 使用块结构矩阵方程，其将输出噪声统计与输入噪声统计相关联。 通过利用Toeplitz块结构，有效的噪声计算方法需要O（nN log N）计算时间和O（nN）存储器，其中n是电路尺寸，N是电路稳态中有效谐波的数量。 该方法使用任意形状的PSD（包括热，射击和闪烁噪声）成功处理设备噪声源，处理噪声输入相关性并计算不同输出之间的相关性。
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10.发明授权Method for supporting multiple libraries characterized at different process, voltage and temperature points 失效支持以不同过程，电压和温度点为特征的多个库的方法公开(公告)号：US08549452B2
公开(公告)日：2013-10-01
申请号：US12774766
申请日：2010-05-06
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5031 , G06F2217/08 , G06F2217/78 , G06F2217/82 , G06F2217/84
摘要： A method for accurately performing a timing, power, and noise analysis by pre-processing the characterization points of the available libraries, storing time consuming parts of the analysis and utilizing the pre-processed information during active runs to calculate the attributes at a desired PVT point. The PVT space is preferably sub-divided into triangular or rectangular regions, preferably obtained using Delaunay triangulation. In one embodiment, the invention performs an up-front pre-processing step on the characterized libraries to compute the static portion of the interpolation function that is independent of the specific instance; and a coefficient matrix that allows for interpolation of specific instances.
摘要翻译： 一种用于通过预处理可用库的表征点来准确地执行定时，功率和噪声分析的方法，存储分析的时间消耗部分并且在主动运行期间利用预处理信息来计算期望PVT处的属性 点。 PVT空间优选地分为三角形或矩形区域，优选地使用Delaunay三角测量法获得。 在一个实施例中，本发明对特征库执行前期预处理步骤，以计算独立于特定实例的内插函数的静态部分; 以及允许特定实例的插值的系数矩阵。
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