公开(公告)号：US20130153960A1

公开(公告)日：2013-06-20

申请号：US13328944

申请日：2011-12-16

申请人： Hsiao-Lan Yang

发明人： Hsiao-Lan Yang

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L27/11206 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5252 ,  H01L27/101 ,  H01L27/115 ,  H01L29/66484 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.

公开(公告)号：US08742457B2

公开(公告)日：2014-06-03

申请号：US13328944

申请日：2011-12-16

申请人： Hsiao-Lan Yang

发明人： Hsiao-Lan Yang

IPC分类号： H01L23/525

CPC分类号： H01L27/11206 ,  H01L21/76895 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/5252 ,  H01L27/101 ,  H01L27/115 ,  H01L29/66484 ,  H01L29/66795 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device includes a substrate, isolation regions at a surface of the substrate, and a semiconductor region over a top surface of the isolation regions. A conductive feature is disposed over the top surface of the isolation regions, wherein the conductive feature is adjacent to the semiconductor region. A dielectric material is disposed between the conductive feature and the semiconductor region. The dielectric material, the conductive feature, and the semiconductor region form an anti-fuse.

摘要翻译： 一种器件包括衬底，衬底表面处的隔离区域以及隔离区域顶表面上的半导体区域。 导电特征设置在隔离区的顶表面上，其中导电特征与半导体区相邻。 介电材料设置在导电特征和半导体区域之间。 电介质材料，导电特征和半导体区域形成反熔丝。

公开(公告)号：US08659090B2

公开(公告)日：2014-02-25

申请号：US13335569

申请日：2011-12-22

申请人： Chia-En Huang ,  Wun-Jie Lin ,  Ling-Chang Hu ,  Hsiao-Lan Yang ,  Chih-Chieh Chiu ,  Wei-Shuo Kao ,  Hong-Chen Cheng ,  Fu-An Wu ,  Jung-Ping Yang ,  Cheng Hung Lee

发明人： Chia-En Huang ,  Wun-Jie Lin ,  Ling-Chang Hu ,  Hsiao-Lan Yang ,  Chih-Chieh Chiu ,  Wei-Shuo Kao ,  Hong-Chen Cheng ,  Fu-An Wu ,  Jung-Ping Yang ,  Cheng Hung Lee

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

摘要： A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.

摘要翻译： 器件包括由半导体材料形成的有源区，有源区的表面处的栅极电介质和栅极电介质上的栅电极。 第一源极/漏极区域和第二源极/漏极区域在栅电极的相对侧上。 接触蚀刻停止层（CESL）位于第一和第二源极/漏极区域之上。 层间电介质（ILD）包括与栅电极的顶表面基本上平齐的顶表面。 第一接触插塞在第一源极/漏极区域上电连接。 第二接触插塞在第二源极/漏极区域之上并对齐。 第二接触插塞和第二源极/漏极区域通过第一CESL的一部分彼此隔开以形成电容器。

公开(公告)号：US20130161707A1

公开(公告)日：2013-06-27

申请号：US13335569

申请日：2011-12-22

申请人： Chia-En Huang ,  Wun-Jie Lin ,  Ling-Chang Hu ,  Hsiao-Lan Yang ,  Chih-Chieh Chiu ,  Wei-Shuo Kao ,  Hong-Chen Cheng ,  Fu-An Wu ,  Jung-Ping Yang ,  Cheng Hung Lee

发明人： Chia-En Huang ,  Wun-Jie Lin ,  Ling-Chang Hu ,  Hsiao-Lan Yang ,  Chih-Chieh Chiu ,  Wei-Shuo Kao ,  Hong-Chen Cheng ,  Fu-An Wu ,  Jung-Ping Yang ,  Cheng Hung Lee

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146

摘要： A device includes an active region formed of a semiconductor material, a gate dielectric at a surface of the active region, and a gate electrode over the gate dielectric. A first source/drain region and a second source/drain region are on opposite sides of the gate electrode. A Contact Etch Stop Layer (CESL) is over the first and the second source/drain regions. An Inter-Layer Dielectric (ILD) includes a top surface substantially level with a top surface of the gate electrode. A first contact plug is over and electrically connected to the first source/drain region. A second contact plug is over and aligned to the second source/drain region. The second contact plug and the second source/drain region are spaced apart from each other by a portion of the first CESL to form a capacitor.

摘要翻译： 器件包括由半导体材料形成的有源区，有源区的表面处的栅极电介质和栅极电介质上的栅电极。 第一源极/漏极区域和第二源极/漏极区域在栅电极的相对侧上。 接触蚀刻停止层（CESL）位于第一和第二源极/漏极区域之上。 层间电介质（ILD）包括与栅电极的顶表面基本上平齐的顶表面。 第一接触插塞在第一源极/漏极区域上电连接。 第二接触插塞在第二源极/漏极区域之上并对齐。 第二接触插塞和第二源极/漏极区域通过第一CESL的一部分彼此隔开以形成电容器。