公开(公告)号：US20080198166A1

公开(公告)日：2008-08-21

申请号：US11675700

申请日：2007-02-16

申请人： Hsine-Chu Chung ,  Chit-Keng Huang ,  Ko-Fang Wang

发明人： Hsine-Chu Chung ,  Chit-Keng Huang ,  Ko-Fang Wang

IPC分类号： G06T1/00

CPC分类号： G06T15/005 ,  G06T2210/52

摘要： A vertex shader. The vertex shader comprises an instruction register file, a flow controller, a thread arbitrator, and an arithmetic logic unit (ALU) pipe. The instruction register file stores a plurality of instructions. The flow controller concurrently executing a plurality of threads, reads the instructions in order from the instruction register file for the threads and accesses vertex data for the threads. The thread arbitrator checks the dependency of instructions in the threads and selects the thread to execute in accordance with the result of the dependency check and a thread execution priority. The arithmetic logic unit (ALU) pipe receives the vertex data for executing the instructions of the thread selected by the thread arbitrator for three-dimensional (3D) graphics computations.

摘要翻译： 顶点着色器 顶点着色器包括指令寄存器文件，流控制器，线程仲裁器和算术逻辑单元（ALU）管道。 指令寄存器文件存储多个指令。 同时执行多个线程的流量控制器从线程的指令寄存器文件中读取指令，并访问线程的顶点数据。 线程仲裁器检查线程中指令的依赖性，并根据依赖性检查的结果和线程执行优先级来选择要执行的线程。 算术逻辑单元（ALU）管接收用于执行由线程仲裁器为三维（3D）图形计算选择的线程的指令的顶点数据。

公开(公告)号：US20080122843A1

公开(公告)日：2008-05-29

申请号：US11458706

申请日：2006-07-20

申请人： Hsine-Chu Chung ,  Ko-Fang Wang ,  Chit-Keng Huang

发明人： Hsine-Chu Chung ,  Ko-Fang Wang ,  Chit-Keng Huang

IPC分类号： G06T15/50 ,  G06F9/312 ,  G06T15/00

CPC分类号： G06T15/005 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/3851 ,  G06T15/80

摘要： A logic unit is provided for performing operations in multiple threads on vertex data. The logic unit comprises a macro instruction register file, a flow control instruction register file, and a flow controller. The macro instruction register file stores macro blocks with each macro block including at least one instruction. The flow control instruction register file stores flow control instructions with each flow control instruction including at least one called macro block and dependency information of the called macro block. The flow controller is configured to perform retrieving the flow control instructions in order from the flow control instruction register file, determining at least one macro block of the macro instruction register file to be executed in accordance with the retrieved flow control instruction and the dependency information thereof, selecting one of the plurality of threads for executing the determined macro block in a predetermined thread schedule policy, and accessing vertex data for the threads.

摘要翻译： 提供了一个用于在顶点数据上的多个线程中执行操作的逻辑单元。 逻辑单元包括宏指令寄存器文件，流控制指令寄存器文件和流控制器。 宏指令寄存器文件存储宏块，每个宏块包括至少一个指令。 流控制指令寄存器文件存储流控制指令，每个流控制指令包括至少一个被叫宏块的被叫宏块和依赖信息。 流控制器被配置为根据流程控制指令寄存器文件依次检索流控制指令，根据检索到的流控制指令及其依赖信息确定要执行的宏指令寄存器文件的至少一个宏块 选择所述多个线程中的一个用于在预定的线程调度策略中执行所确定的宏块，以及访问所述线程的顶点数据。