公开(公告)号：US20110051009A1

公开(公告)日：2011-03-03

申请号：US12841442

申请日：2010-07-22

申请人： Kun-Nan Cheng ,  Chih-Tien Chang ,  Chit-Keng Huang

发明人： Kun-Nan Cheng ,  Chih-Tien Chang ,  Chit-Keng Huang

IPC分类号： H04N5/14

CPC分类号： H04N5/144 ,  H04N5/04

摘要： An auto phase detection apparatus for automatically detecting a target sampling phase is provided. The auto phase detection apparatus includes a phase decider for generating a plurality of phase control signals; a sample clock generator, coupled to the phase decider, for generating a plurality of sample clock signals according to the phase control signals; an analog-to-digital converter (ADC), coupled to the sample clock generator, for converting an analog video signal to a digital signal according to the sample clock signals; a phase detector, coupled to the ADC and the phase decider, for generating a plurality of phase detection results according to the digital signal; and a motion detector, coupled to the ADC and the phase decider, for generating a motion detection result by detecting a motion in the digital signal. The phase decider determines the target sampling phase from the phase control signals according to the phase detection results and the motion detection result.

摘要翻译： 提供了一种用于自动检测目标采样相位的自动相位检测装置。 自动相位检测装置包括用于产生多个相位控制信号的相位判定器; 耦合到相位决定器的采样时钟发生器，用于根据相位控制信号产生多个采样时钟信号; 耦合到采样时钟发生器的模数转换器（ADC），用于根据采样时钟信号将模拟视频信号转换成数字信号; 耦合到ADC和相位决定器的相位检测器，用于根据数字信号产生多个相位检测结果; 以及耦合到ADC和相位决定器的运动检测器，用于通过检测数字信号中的运动来产生运动检测结果。 相位决定器根据相位检测结果和运动检测结果根据相位控制信号确定目标采样相位。

公开(公告)号：US09197876B2

公开(公告)日：2015-11-24

申请号：US12868831

申请日：2010-08-26

申请人： Kun-Nan Cheng ,  Chit-Keng Huang ,  Yi-Chung Liao

发明人： Kun-Nan Cheng ,  Chit-Keng Huang ,  Yi-Chung Liao

IPC分类号： H04N13/00

CPC分类号： H04N13/167 ,  H04N13/139

摘要： A frame rate conversion apparatus for 3D display is provided. The frame rate conversion apparatus for 3D display is capable of preserving alternate display of left and right frames while also preventing an issue of frame tearing. The frame rate conversion apparatus includes a storage unit, an input controller and an output controller. The input controller inputs an input frame sequence to the storage unit according to an input frame rate. The input frame sequence includes a plurality of frame pairs each having a left frame and a corresponding right frame. The output controller alternately outputs one of the left frames and one of the right frames from the storage unit according to an output frame rate and left/right frame information associated with the frame pairs in the storage unit to form an output frame sequence.

摘要翻译： 提供了一种用于3D显示的帧速率转换装置。 用于3D显示的帧速率转换装置能够保持左右帧的交替显示，同时也防止帧撕裂的发生。 帧率转换装置包括存储单元，输入控制器和输出控制器。 输入控制器根据输入帧速率将输入帧序列输入到存储单元。 输入帧序列包括多个帧对，每一帧具有左帧和对应的右帧。 输出控制器根据与存储单元中的帧对相关联的输出帧速率和左/右帧信息从存储单元交替地输出左帧和右帧之一，以形成输出帧序列。

公开(公告)号：US20110050862A1

公开(公告)日：2011-03-03

申请号：US12868831

申请日：2010-08-26

申请人： Kun-Nan Cheng ,  Chit-Keng Huang ,  Yi-Chung Liao

发明人： Kun-Nan Cheng ,  Chit-Keng Huang ,  Yi-Chung Liao

IPC分类号： H04N13/04

CPC分类号： H04N13/167 ,  H04N13/139

摘要： A frame rate conversion apparatus for 3D display is provided. The frame rate conversion apparatus for 3D display is capable of preserving alternate display of left and right frames while also preventing an issue of frame tearing. The frame rate conversion apparatus includes a storage unit, an input controller and an output controller. The input controller inputs an input frame sequence to the storage unit according to an input frame rate. The input frame sequence includes a plurality of frame pairs each having a left frame and a corresponding right frame. The output controller alternately outputs one of the left frames and one of the right frames from the storage unit according to an output frame rate and left/right frame information associated with the frame pairs in the storage unit to form an output frame sequence.

摘要翻译： 提供了一种用于3D显示的帧速率转换装置。 用于3D显示的帧速率转换装置能够保持左右帧的交替显示，同时也防止帧撕裂的发生。 帧率转换装置包括存储单元，输入控制器和输出控制器。 输入控制器根据输入帧速率将输入帧序列输入到存储单元。 输入帧序列包括多个帧对，每一帧具有左帧和对应的右帧。 输出控制器根据与存储单元中的帧对相关联的输出帧速率和左/右帧信息从存储单元交替地输出左帧和右帧之一，以形成输出帧序列。

公开(公告)号：US08848795B2

公开(公告)日：2014-09-30

申请号：US12841442

申请日：2010-07-22

申请人： Kun-Nan Cheng ,  Chih-Tien Chang ,  Chit-Keng Huang

发明人： Kun-Nan Cheng ,  Chih-Tien Chang ,  Chit-Keng Huang

IPC分类号： H04N7/12 ,  H04N5/14 ,  H04N5/04

CPC分类号： H04N5/144 ,  H04N5/04

摘要： An auto phase detection apparatus for automatically detecting a target sampling phase is provided. The auto phase detection apparatus includes a phase decider for generating a plurality of phase control signals; a sample clock generator, coupled to the phase decider, for generating a plurality of sample clock signals according to the phase control signals; an analog-to-digital converter (ADC), coupled to the sample clock generator, for converting an analog video signal to a digital signal according to the sample clock signals; a phase detector, coupled to the ADC and the phase decider, for generating a plurality of phase detection results according to the digital signal; and a motion detector, coupled to the ADC and the phase decider, for generating a motion detection result by detecting a motion in the digital signal. The phase decider determines the target sampling phase from the phase control signals according to the phase detection results and the motion detection result.

摘要翻译： 提供了一种用于自动检测目标采样相位的自动相位检测装置。 自动相位检测装置包括用于产生多个相位控制信号的相位判定器; 耦合到相位决定器的采样时钟发生器，用于根据相位控制信号产生多个采样时钟信号; 耦合到采样时钟发生器的模数转换器（ADC），用于根据采样时钟信号将模拟视频信号转换成数字信号; 耦合到ADC和相位决定器的相位检测器，用于根据数字信号产生多个相位检测结果; 以及耦合到ADC和相位决定器的运动检测器，用于通过检测数字信号中的运动来产生运动检测结果。 相位决定器根据相位检测结果和运动检测结果根据相位控制信号确定目标采样相位。

公开(公告)号：US20080198166A1

公开(公告)日：2008-08-21

申请号：US11675700

申请日：2007-02-16

申请人： Hsine-Chu Chung ,  Chit-Keng Huang ,  Ko-Fang Wang

发明人： Hsine-Chu Chung ,  Chit-Keng Huang ,  Ko-Fang Wang

IPC分类号： G06T1/00

CPC分类号： G06T15/005 ,  G06T2210/52

摘要： A vertex shader. The vertex shader comprises an instruction register file, a flow controller, a thread arbitrator, and an arithmetic logic unit (ALU) pipe. The instruction register file stores a plurality of instructions. The flow controller concurrently executing a plurality of threads, reads the instructions in order from the instruction register file for the threads and accesses vertex data for the threads. The thread arbitrator checks the dependency of instructions in the threads and selects the thread to execute in accordance with the result of the dependency check and a thread execution priority. The arithmetic logic unit (ALU) pipe receives the vertex data for executing the instructions of the thread selected by the thread arbitrator for three-dimensional (3D) graphics computations.

摘要翻译： 顶点着色器 顶点着色器包括指令寄存器文件，流控制器，线程仲裁器和算术逻辑单元（ALU）管道。 指令寄存器文件存储多个指令。 同时执行多个线程的流量控制器从线程的指令寄存器文件中读取指令，并访问线程的顶点数据。 线程仲裁器检查线程中指令的依赖性，并根据依赖性检查的结果和线程执行优先级来选择要执行的线程。 算术逻辑单元（ALU）管接收用于执行由线程仲裁器为三维（3D）图形计算选择的线程的指令的顶点数据。

公开(公告)号：US20080122843A1

公开(公告)日：2008-05-29

申请号：US11458706

申请日：2006-07-20

申请人： Hsine-Chu Chung ,  Ko-Fang Wang ,  Chit-Keng Huang

发明人： Hsine-Chu Chung ,  Ko-Fang Wang ,  Chit-Keng Huang

IPC分类号： G06T15/50 ,  G06F9/312 ,  G06T15/00

CPC分类号： G06T15/005 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3838 ,  G06F9/3851 ,  G06T15/80

摘要： A logic unit is provided for performing operations in multiple threads on vertex data. The logic unit comprises a macro instruction register file, a flow control instruction register file, and a flow controller. The macro instruction register file stores macro blocks with each macro block including at least one instruction. The flow control instruction register file stores flow control instructions with each flow control instruction including at least one called macro block and dependency information of the called macro block. The flow controller is configured to perform retrieving the flow control instructions in order from the flow control instruction register file, determining at least one macro block of the macro instruction register file to be executed in accordance with the retrieved flow control instruction and the dependency information thereof, selecting one of the plurality of threads for executing the determined macro block in a predetermined thread schedule policy, and accessing vertex data for the threads.

摘要翻译： 提供了一个用于在顶点数据上的多个线程中执行操作的逻辑单元。 逻辑单元包括宏指令寄存器文件，流控制指令寄存器文件和流控制器。 宏指令寄存器文件存储宏块，每个宏块包括至少一个指令。 流控制指令寄存器文件存储流控制指令，每个流控制指令包括至少一个被叫宏块的被叫宏块和依赖信息。 流控制器被配置为根据流程控制指令寄存器文件依次检索流控制指令，根据检索到的流控制指令及其依赖信息确定要执行的宏指令寄存器文件的至少一个宏块 选择所述多个线程中的一个用于在预定的线程调度策略中执行所确定的宏块，以及访问所述线程的顶点数据。