公开(公告)号：US07257791B2

公开(公告)日：2007-08-14

申请号：US10992999

申请日：2004-11-19

申请人： Alexei V. Galatenko ,  Elyar E. Gasanov ,  Andrej A. Zolotykh ,  Iliya V. Lyalin

发明人： Alexei V. Galatenko ,  Elyar E. Gasanov ,  Andrej A. Zolotykh ,  Iliya V. Lyalin

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Buffers are inserted into an integrated circuit chip design using a table that identifies buffer types based on buffer height, input capacitance, output capacitance and ramptime. A buffer routing tree is created having root, internal and leaf vertices. For each internal vertex, the initial circuit parameters are compared to circuit parameters associated with buffers identified in the table to identify whether a buffer identified in the table can be inserted to the respective internal vertex. If it can, an optimal insertable buffer is selected from the table and inserted to a selected internal vertex based at least in part on the comparison results. Also described is a computer process of creating the buffer type table.

摘要翻译： 使用基于缓冲器高度，输入电容，输出电容和延迟时间来识别缓冲器类型的表，将缓冲器插入到集成电路芯片设计中。 创建具有根，内部和叶子顶点的缓冲区路由树。 对于每个内部顶点，将初始电路参数与与表中标识的缓冲器相关联的电路参数进行比较，以识别表中识别的缓冲区是否可以插入到相应的内部顶点。 如果可以，则至少部分地基于比较结果，从表中选择最佳可插入缓冲器并将其插入到选定的内部顶点。 还描述了创建缓冲器类型表的计算机处理。

公开(公告)号：US07146591B2

公开(公告)日：2006-12-05

申请号：US10992941

申请日：2004-11-19

申请人： Iliya V. Lyalin ,  Andrej A. Zolotykh ,  Elyar E. Gasanov ,  Alexei V. Galatenko

发明人： Iliya V. Lyalin ,  Andrej A. Zolotykh ,  Elyar E. Gasanov ,  Alexei V. Galatenko

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/505

摘要： The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.

公开(公告)号：US07401313B2

公开(公告)日：2008-07-15

申请号：US11258738

申请日：2005-10-26

申请人： Alexei V. Galatenko ,  Elyar E. Gasanov ,  Iliya V. Lyalin

发明人： Alexei V. Galatenko ,  Elyar E. Gasanov ,  Iliya V. Lyalin

IPC分类号： G06F17/50 ,  G06F7/00

CPC分类号： G06F17/5045 ,  G06F17/5077 ,  G06F2217/84

摘要： The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing congestion value is estimated for each congestion rectangle prior to routing interconnections within the design field. The congestion values are stored in machine-readable memory and are updated in response to wire changes within the design field.

摘要翻译： 本公开涉及一种用于将集成电路设计字段划分为具有用户可选择尺寸的多个拥塞矩形的方法和装置。 在设计字段内路由互连之前，为每个拥塞矩形估计路由拥塞值。 拥塞值存储在机器可读存储器中，并响应于设计领域内的线路更改而被更新。

公开(公告)号：US07111267B2

公开(公告)日：2006-09-19

申请号：US10928799

申请日：2004-08-27

申请人： Elyar E. Gasanov ,  Iliya V. Lyalin ,  Alexei V. Galatenko ,  Andrej A. Zolotykh

发明人： Elyar E. Gasanov ,  Iliya V. Lyalin ,  Alexei V. Galatenko ,  Andrej A. Zolotykh

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： An iterative process assigns nodes of a new logical tree to positions in a space that was previously assigned to an old logical tree equivalent to the new logical tree. A path in the new tree is identified for an essential node of the new tree. Coordinates of a position in the space are identified for an old tree node that is equivalent to a son of the essential node. Coordinates are iteratively identified for each node in the new tree path using a free space algorithm and based on the nodes of the new tree path and the coordinates identified for the old tree node that is equivalent to the son of the essential node. If all sons of the essential node are leaves of the new tree, the old tree node is a leaf node equivalent to the son. Otherwise, the old tree node is identified in a prior iteration.

摘要翻译： 迭代过程将新逻辑树的节点分配给先前分配给等同于新逻辑树的旧逻辑树的空间中的位置。 新树中的路径被标识为新树的基本节点。 为相当于基本节点的子节点的旧树节点识别空间位置的坐标。 使用自由空间算法并且基于新树路径的节点和为相同于基本节点的儿子的旧树节点识别的坐标，迭代地识别新树路径中的每个节点的坐标。 如果基本节点的所有儿子都是新树的叶子，那么旧的树节点就是与子节点相当的叶节点。 否则，在先前的迭代中识别旧树节点。

公开(公告)号：US07496870B2

公开(公告)日：2009-02-24

申请号：US11551573

申请日：2006-10-20

申请人： Iliya V. Lyalin ,  Andrej A. Zolotykh ,  Elyar E. Gasanov ,  Alexei V. Galatenko

发明人： Iliya V. Lyalin ,  Andrej A. Zolotykh ,  Elyar E. Gasanov ,  Alexei V. Galatenko

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.

摘要翻译： 本公开涉及一种用于选择用于原始设计的逻辑重组的集成电路中的单元的方法。 原始设计包括一组参数。 该方法包括形成将包括用于逻辑重组的所选择的单元的重构集合和候选集。 重组集合包括具有初始单元格的重组单元。 重组集合适于接受被称为重组细胞的额外细胞。 候选集合适于包括候选小区，其中候选集合中的每个候选小区连接到重组集合中的至少一个重组小区。 候选集合适于从候选集中移除候选细胞。 如果在参数集合中包括相应的参数，则重组集合适于接受所选择的被移除的候选小区作为已识别的重组小区。