公开(公告)号：US20120226731A1

公开(公告)日：2012-09-06

申请号：US13231129

申请日：2011-09-13

申请人： Sergey B. Gashkov ,  Anatoli A. Bolotov ,  Mikhail I. Grinchuk ,  Lav D. Ivanovic ,  Anatoly A. Chasovshikh ,  Alexei V. Galatenko ,  Igor V. Kucherenko

发明人： Sergey B. Gashkov ,  Anatoli A. Bolotov ,  Mikhail I. Grinchuk ,  Lav D. Ivanovic ,  Anatoly A. Chasovshikh ,  Alexei V. Galatenko ,  Igor V. Kucherenko

IPC分类号： G06F7/523

CPC分类号： G06F7/724 ,  G06F17/505

摘要： A method for generating a design of a multiplier is disclosed. The method generally includes steps (A) to (C). Step (A) may generate a first circuit comprising a plurality of polynomial results of a particular multiplier scheme based on a plurality of parameters of the multiplier. The first circuit is generally configured to multiply a plurality of polynomials. Step (B) may generate a second circuit comprising a plurality of polynomial evaluators based on the parameters. The second circuit may be (i) connected to the first circuit and (ii) configured to evaluate a polynomial modulo operation. Step (C) may generate the design of the multiplier in combinational logic by optimizing a depth of a plurality of logic gates through the first circuit and the second circuit. A product of the polynomials generally resides in a finite field.

摘要翻译： 公开了一种生成乘法器设计的方法。 该方法通常包括步骤（A）至（C）。 步骤（A）可以基于乘法器的多个参数来生成包括特定乘法器方案的多个多项式结果的第一电路。 第一电路通常被配置为乘以多个多项式。 步骤（B）可以基于参数生成包括多个多项式评估器的第二电路。 第二电路可以是（i）连接到第一电路，（ii）被配置为评估多项式模运算。 步骤（C）可以通过优化通过第一电路和第二电路的多个逻辑门的深度来生成组合逻辑中乘法器的设计。 多项式的乘积通常位于有限域中。

公开(公告)号：US20100086127A1

公开(公告)日：2010-04-08

申请号：US12246812

申请日：2008-10-07

申请人： Mikhail Grinchuk ,  Anatoli Bolotov ,  Lav D. Ivanovic ,  Andrej A. Zolotykh ,  Alexei V. Galatenko

发明人： Mikhail Grinchuk ,  Anatoli Bolotov ,  Lav D. Ivanovic ,  Andrej A. Zolotykh ,  Alexei V. Galatenko

IPC分类号： H04L9/06

CPC分类号： H04L9/0643 ,  H04L2209/125

摘要： An apparatus including an initialization circuit and a hash computation circuit. The initialization circuit may be configured to present a number of initialization values. The hash computation circuit may be configured to generate hash values for the message in response to the padded message blocks and the initialization values. The hash computation circuit generally performs a diagonal cut technique that simultaneously uses values from a plurality of different cycle rounds in a single cycle round analog.

摘要翻译： 一种包括初始化电路和散列计算电路的装置。 初始化电路可以被配置为呈现多个初始化值。 哈希计算电路可以被配置为响应于填充的消息块和初始化值来生成消息的散列值。 哈希计算电路通常执行对角切割技术，其同时使用来自单周期循环模拟中的多个不同循环回合的值。

公开(公告)号：US07401313B2

公开(公告)日：2008-07-15

申请号：US11258738

申请日：2005-10-26

申请人： Alexei V. Galatenko ,  Elyar E. Gasanov ,  Iliya V. Lyalin

发明人： Alexei V. Galatenko ,  Elyar E. Gasanov ,  Iliya V. Lyalin

IPC分类号： G06F17/50 ,  G06F7/00

CPC分类号： G06F17/5045 ,  G06F17/5077 ,  G06F2217/84

摘要： The present disclosure is directed to a method and apparatus for dividing an integrated circuit design field into a plurality of congestion rectangles having user-selectable sizes. A routing congestion value is estimated for each congestion rectangle prior to routing interconnections within the design field. The congestion values are stored in machine-readable memory and are updated in response to wire changes within the design field.

摘要翻译： 本公开涉及一种用于将集成电路设计字段划分为具有用户可选择尺寸的多个拥塞矩形的方法和装置。 在设计字段内路由互连之前，为每个拥塞矩形估计路由拥塞值。 拥塞值存储在机器可读存储器中，并响应于设计领域内的线路更改而被更新。

公开(公告)号：US07257791B2

公开(公告)日：2007-08-14

申请号：US10992999

申请日：2004-11-19

申请人： Alexei V. Galatenko ,  Elyar E. Gasanov ,  Andrej A. Zolotykh ,  Iliya V. Lyalin

发明人： Alexei V. Galatenko ,  Elyar E. Gasanov ,  Andrej A. Zolotykh ,  Iliya V. Lyalin

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： Buffers are inserted into an integrated circuit chip design using a table that identifies buffer types based on buffer height, input capacitance, output capacitance and ramptime. A buffer routing tree is created having root, internal and leaf vertices. For each internal vertex, the initial circuit parameters are compared to circuit parameters associated with buffers identified in the table to identify whether a buffer identified in the table can be inserted to the respective internal vertex. If it can, an optimal insertable buffer is selected from the table and inserted to a selected internal vertex based at least in part on the comparison results. Also described is a computer process of creating the buffer type table.

摘要翻译： 使用基于缓冲器高度，输入电容，输出电容和延迟时间来识别缓冲器类型的表，将缓冲器插入到集成电路芯片设计中。 创建具有根，内部和叶子顶点的缓冲区路由树。 对于每个内部顶点，将初始电路参数与与表中标识的缓冲器相关联的电路参数进行比较，以识别表中识别的缓冲区是否可以插入到相应的内部顶点。 如果可以，则至少部分地基于比较结果，从表中选择最佳可插入缓冲器并将其插入到选定的内部顶点。 还描述了创建缓冲器类型表的计算机处理。

公开(公告)号：US07246336B2

公开(公告)日：2007-07-17

申请号：US11004309

申请日：2004-12-03

申请人： Andrej A. Zolotykh ,  Elyar E. Gasanov ,  Alexei V. Galatenko ,  Ilya V. Lyalin

发明人： Andrej A. Zolotykh ,  Elyar E. Gasanov ,  Alexei V. Galatenko ,  Ilya V. Lyalin

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.

摘要翻译： 描述了一种用于计算具有在一个或多个闭合回路中的定向图中互连的引脚的集成电路布图图案的突发时间传播的方法。 对于第一组引脚计算Ramptime值，它们不连接到闭环，同时留下第二组引脚具有未知的ramptime值。 一个或多个闭环通过从第二组中的引脚回溯具有未知的ramptime值来识别。 迭代地计算一个或多个闭环中每个引脚的ramptime值。

公开(公告)号：US07146591B2

公开(公告)日：2006-12-05

申请号：US10992941

申请日：2004-11-19

申请人： Iliya V. Lyalin ,  Andrej A. Zolotykh ,  Elyar E. Gasanov ,  Alexei V. Galatenko

发明人： Iliya V. Lyalin ,  Andrej A. Zolotykh ,  Elyar E. Gasanov ,  Alexei V. Galatenko

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/505

摘要： The present disclosure is directed to a method of selecting cells in an integrated circuit for logic restructuring of an original design. The original design includes a set of parameters. The method includes forming a restructuring set that will include the selected cells for logic restructuring, and a candidate set. The restructuring set includes restructuring cells with an initial cell. The restructuring set is adapted to accept additional cells identified as restructuring cells. The candidate set is adapted to include candidate cells, where each candidate cell in the candidate set is connected to at least one of the restructuring cells in the restructuring set. The candidate set is adapted to remove candidate cells from the candidate set. The restructuring set is adapted to accept selected removed candidate cells as identified restructuring cells if a corresponding parameter is included in the set of parameters.

公开(公告)号：US07568175B2

公开(公告)日：2009-07-28

申请号：US11757229

申请日：2007-06-01

申请人： Andrej A. Zolotykh ,  Elyar E. Gasanov ,  Alexei V. Galatenko ,  Ilya V. Lyalin

发明人： Andrej A. Zolotykh ,  Elyar E. Gasanov ,  Alexei V. Galatenko ,  Ilya V. Lyalin

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A method and apparatus for calculating ramptime propagation for integrated circuit layout patterns having pins interconnected in an oriented graph in one or more closed loops is described. Ramptime values are calculated for a first set of the pins, which are not connected to a closed loop while leaving a second set of the pins with unknown ramptime values. One or more closed loops are identified by backtracking from the pins in the second set with unknown ramptime values. A ramptime value for each pin in the one or more closed loops is calculated iteratively.

摘要翻译： 描述了一种用于计算具有在一个或多个闭环中的定向图中互连的引脚的集成电路布图图案的突触传播的方法和装置。 对于第一组引脚计算Ramptime值，它们不连接到闭环，同时留下第二组引脚具有未知的ramptime值。 一个或多个闭环通过从第二组中的引脚回溯具有未知的ramptime值来识别。 迭代地计算一个或多个闭环中每个引脚的ramptime值。

公开(公告)号：US07111267B2

公开(公告)日：2006-09-19

申请号：US10928799

申请日：2004-08-27

申请人： Elyar E. Gasanov ,  Iliya V. Lyalin ,  Alexei V. Galatenko ,  Andrej A. Zolotykh

发明人： Elyar E. Gasanov ,  Iliya V. Lyalin ,  Alexei V. Galatenko ,  Andrej A. Zolotykh

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： An iterative process assigns nodes of a new logical tree to positions in a space that was previously assigned to an old logical tree equivalent to the new logical tree. A path in the new tree is identified for an essential node of the new tree. Coordinates of a position in the space are identified for an old tree node that is equivalent to a son of the essential node. Coordinates are iteratively identified for each node in the new tree path using a free space algorithm and based on the nodes of the new tree path and the coordinates identified for the old tree node that is equivalent to the son of the essential node. If all sons of the essential node are leaves of the new tree, the old tree node is a leaf node equivalent to the son. Otherwise, the old tree node is identified in a prior iteration.

摘要翻译： 迭代过程将新逻辑树的节点分配给先前分配给等同于新逻辑树的旧逻辑树的空间中的位置。 新树中的路径被标识为新树的基本节点。 为相当于基本节点的子节点的旧树节点识别空间位置的坐标。 使用自由空间算法并且基于新树路径的节点和为相同于基本节点的儿子的旧树节点识别的坐标，迭代地识别新树路径中的每个节点的坐标。 如果基本节点的所有儿子都是新树的叶子，那么旧的树节点就是与子节点相当的叶节点。 否则，在先前的迭代中识别旧树节点。

公开(公告)号：US07398486B2

公开(公告)日：2008-07-08

申请号：US10803516

申请日：2004-03-17

申请人： Alexei V. Galatenko ,  Elyar E. Gasanov ,  Andrej A. Zolotykh

发明人： Alexei V. Galatenko ,  Elyar E. Gasanov ,  Andrej A. Zolotykh

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5077

摘要： The present invention provides a new approach and algorithm to optimize various design parameters in global routing. According to an exemplary aspect of the present invention, marked trees are first preprocessed. For every vertex incident to leaves, one may go through the list of its leaves, and if two leaves have the same mark one may leave only one of them. After that whether homeomorphism exists may be determined. The reason behind selecting such homeomorphic pairs is as follows: adding or removing a vertex of degree 2 as well as adding or removing a new leaf (variable) does not significantly modify routing (in this case all routing transformations are in essence splitting and merging routing trees). After the selection of applicable transformations, one may apply them to optimize design parameters. This may be achieved by assigning the same coordinates to nodes of degree !=2 of homeomorphic trees, which means that one may assign the coordinates of corresponding nodes to “essential” nodes and then insert or remove nodes of degree 2.

摘要翻译： 本发明提供了一种用于优化全局路由中的各种设计参数的新方法和算法。 根据本发明的示例性方面，首先对标记的树进行预处理。 对于每个离开的顶点，可以通过它的叶子列表，如果两个叶子有相同的标记，那么可以只留下其中一个。 之后，可以确定是否存在同胚。 选择这种同胚对之后的原因如下：添加或删除2级顶点以及添加或删除新叶（变量）不会显着修改路由（在这种情况下，所有路由转换本质上都是分割和合并路由 树）。 选择适用的变换后，可以应用它们来优化设计参数。 这可以通过将相同的坐标分配给同胚树的度数= 2的节点来实现，这意味着可以将对应节点的坐标分配给“必需”节点，然后插入或移除度数2的节点。

公开(公告)号：US07103865B2

公开(公告)日：2006-09-05

申请号：US10719393

申请日：2003-11-21

申请人： Alexei V. Galatenko ,  Valeriy B. Kudryavtsev ,  Elyar E. Gasanov

发明人： Alexei V. Galatenko ,  Valeriy B. Kudryavtsev ,  Elyar E. Gasanov

IPC分类号： G06F9/45 ,  G06F17/50

CPC分类号： G06F17/5072

摘要： An IC layout containing megacells placed in violation of design rules is corrected to remove design rule violations while maintaining the original placement as near as practical. The sizes of at least some of the megacells are inflated. The megacells are placed and moved in a footprint of the circuit in a manner to reduce placement complexity. The placement of the megacells is permuted to reduce placement complexity. Additional movements are be applied to the permuted placement to further reduce placement complexity.

摘要翻译： 包含违反设计规则的大型电力设备的IC布局被更正，以消除设计规则违规，同时将原始位置保持在可接近的范围内。 至少一些大型电池的尺寸是膨胀的。 这些巨型电池以一种降低放置复杂性的方式放置并移动到电路的占位面积中。 大容量的放置被置换以减少放置复杂性。 额外的运动可应用于排列的位置，以进一步降低放置复杂性。