公开(公告)号：US5124585A

公开(公告)日：1992-06-23

申请号：US642077

申请日：1991-01-16

Applicant: Jun Kim ,  In-Nan Wu

Inventor： Jun Kim ,  In-Nan Wu

IPC: H03K19/017

CPC classification number: H03K19/01714

Abstract: An output buffer circuit is provided for use with a first external voltage which provides voltage at a first level, the output buffer circuit comprising: an output terminal; a second voltage supply for providing voltage at a second level less than the first level; an n-channel pull-up transistor including a drain coupled to the first voltage supply and including a source coupled to the output terminal; a p-channel pull-up transistor including a drain coupled to the output terminal and a source coupled to the second voltage supply; an n-channel pull-down transistor including a drain coupled to the output terminal; a bootstrapping turn-on circuit for raising a gate of the n-channel pull-up transistor to a raised voltage level which is above the first voltage level such that the n-channel pull-up transistor becomes turned on; a turn-off circuit for turning off the n-channel pull-up transistor when the output terminal has been substantially pulled up to the second voltage level; and a turn-on circuit for turning on the p-channel pull-up transistor when the output voltage at the output terminal has been substantially pulled up to the second level.

Abstract translation: 输出缓冲电路用于提供第一电平的第一外部电压，所述输出缓冲电路包括：输出端; 第二电压源，用于提供小于第一电平的第二电平的电压; n沟道上拉晶体管，其包括耦合到所述第一电压源并且包括耦合到所述输出端子的源极的漏极; p沟道上拉晶体管，其包括耦合到所述输出端子的漏极和耦合到所述第二电压源的源极; n沟道下拉晶体管，其包括耦合到所述输出端子的漏极; 用于将n沟道上拉晶体管的栅极升高到高于第一电压电平的升高电压电平的自举导通电路，使得n沟道上拉晶体管导通; 当输出端基本上升到第二电压电平时关断n沟道上拉晶体管的截止电路; 以及当输出端子处的输出电压基本上升到第二电平时导通p沟道上拉晶体管的导通电路。

公开(公告)号：US5001671A

公开(公告)日：1991-03-19

申请号：US372072

申请日：1989-06-27

Applicant: James T. Koo ,  In-Nan Wu ,  Francis C. Hung ,  King Wang ,  Jon C. Zierk

Inventor： James T. Koo ,  In-Nan Wu ,  Francis C. Hung ,  King Wang ,  Jon C. Zierk

IPC: G11C8/16 ,  G11C8/18

CPC classification number: G11C8/16 ,  G11C8/18

Abstract: The present invention is a controller for producing a dual port function from a single port memory with an improved memory cycle time. An address or control signal transition for one port generates an access request signal for that port. The access request signal both (1) blocks an access request by the other port for its duration and (2) generates a series of signals for a memory access for the selected port. A multiplexer for providing addresses to the memory core from two ports is switched to select a second port while a first port access is in progress. The output of the multiplexer is not enabled until the memory core access is completed. Thus, the set-up time for the second set of addresses is allowed to overlap the memory core access time for the first set of addresses thereby reducing overall cycle time.

Abstract translation: 本发明是一种用于从具有改进的存储周期时间的单个端口存储器产生双端口功能的控制器。 一个端口的地址或控制信号转换产生该端口的访问请求信号。 访问请求信号（1）在其持续时间内阻止另一端口的访问请求;（2）生成用于所选端口的存储器访问的一系列信号。 在第一端口访问正在进行时，用于从两个端口向存储器核提供地址的复用器被切换以选择第二端口。 直到内存核心访问完成，多路复用器的输出才能使能。 因此，允许第二组地址的建立时间与第一组地址的存储器核心访问时间重叠，从而减少总体周期时间。

公开(公告)号：US5233699A

公开(公告)日：1993-08-03

申请号：US325554

申请日：1989-03-17

Applicant: In-Nan Wu ,  James T. Koo ,  Kong-Yeu Han

Inventor： In-Nan Wu ,  James T. Koo ,  Kong-Yeu Han

IPC: G06F12/08

CPC classification number: G06F12/0802

Abstract: The present invention provides an extended memory capability without requiring a much faster cache memory. This is done by providing address latches on the same chip as the cache memory and providing the most significant address bit from the address latches to be combined with the output of appropriate interface logic. The result of this combination is provided as address control signal along a path to the memory which does not require as long an access time as the rest of the addresses.

Abstract translation: 本发明提供了扩展的存储器能力，而不需要更快的高速缓冲存储器。 这通过在与高速缓冲存储器相同的芯片上提供地址锁存器并且从地址锁存器提供最高有效地址位以与适当的接口逻辑的输出组合来完成。 该组合的结果被提供为沿着到存储器的路径的地址控制信号，其不需要与其余地址一样长的访问时间。