公开(公告)号：US20090217075A1

公开(公告)日：2009-08-27

申请号：US12034896

申请日：2008-02-21

申请人： Etai Adar ,  Ilya Granovsky ,  Efrat Greenberg ,  Itay Poleg

发明人： Etai Adar ,  Ilya Granovsky ,  Efrat Greenberg ,  Itay Poleg

IPC分类号： G06F1/04

CPC分类号： G06F1/12 ,  G01R31/31726 ,  G01R31/31727 ,  G01R31/31937

摘要： The present invention implements a mechanism which enables zero-delay verification tools to detect clock domain crossing violation in device under test designs comprising two different clock domains where the fast clock is an integer multiple of the slow clock by inserting undefined (i.e., invalid) values on slow clock domain signals during the clock periods when the signals are not supposed to be captured. The undefined values are contained in the logic cone and emulate timing uncertainly of the path. Propagation of the undefined values through the capturing latch indicates improper clock domains crossing handling.

摘要翻译： 本发明实现了一种使得零延迟验证工具能够检测包括两个不同时钟域的设备中的时钟域交叉违规的机制，其中快速时钟是慢时钟的整数倍，通过插入未定义的（即，无效的）值 在不应该捕获信号的时钟周期内的慢时钟域信号。 未定义的值包含在逻辑锥中，并且不确定地模拟路径的时序。 通过捕获锁存器传播未定义的值表示不正确的时钟域穿越处理。

公开(公告)号：US08024597B2

公开(公告)日：2011-09-20

申请号：US12034896

申请日：2008-02-21

申请人： Etai Adar ,  Ilya Granovsky ,  Efrat Greenberg ,  Itay Poleg

发明人： Etai Adar ,  Ilya Granovsky ,  Efrat Greenberg ,  Itay Poleg

IPC分类号： G06F1/04

CPC分类号： G06F1/12 ,  G01R31/31726 ,  G01R31/31727 ,  G01R31/31937

摘要： The present invention implements a mechanism which enables zero-delay verification tools to detect clock domain crossing violations in device under test designs comprising two different clock domains where the fast clock rate is an integer multiple of the slow clock rate by inserting undefined (i.e., invalid) values on slow clock domain signals during the clock periods when the signals are not supposed to be captured. The undefined values are contained in the logic cone and emulate timing uncertainty of the path. Propagation of the undefined values through the capturing latch indicates improper clock domains crossing handling.

摘要翻译： 本发明实现了一种使得零延迟验证工具能够检测包括两个不同时钟域的设备中的时钟域交叉违反的机制，其中快速时钟速率是通过插入未定义的（即，无效的 ）时钟周期内的慢时钟域信号值。 未定义的值包含在逻辑锥中并模拟路径的时序不确定度。 通过捕获锁存器传播未定义的值表示不正确的时钟域穿越处理。