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公开(公告)号：US07353484B1
公开(公告)日：2008-04-01
申请号：US10775966
申请日：2004-02-09
申请人： J. Orion Pritchard , Todd Wayne
发明人： J. Orion Pritchard , Todd Wayne
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Methods and apparatus are provided for interconnecting primary components with secondary components on a programmable chip. Control, data, and address lines are automatically generated to connect primary components and secondary components with an interconnection module. The interconnection connection module manages interaction between primary components and secondary components and provides support for fixed latency and variable latency secondary components.
摘要翻译： 提供了用于将主要组件与可编程芯片上的次要组件互连的方法和装置。 自动生成控制，数据和地址线，以连接主组件和辅助组件与互连模块。 互连连接模块管理主要组件和次要组件之间的交互，并为固定延迟和可变延迟次要组件提供支持。
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公开(公告)号：US07149827B1
公开(公告)日：2006-12-12
申请号：US10775994
申请日：2004-02-09
申请人： J. Orion Pritchard , Todd Wayne
发明人： J. Orion Pritchard , Todd Wayne
CPC分类号： G06F13/1605 , G06F13/1684
摘要： Methods and apparatus are provided for interconnecting on-chip components, such as components on a programmable chip, with off-chip components through a variety of buses, fabrics, and input/output lines. Interconnection resources such as input/output lines are shared for communication with different off-chip components such as memory. Control circuitry and an arbitration fabric are provided to further improve communication efficiency between on-chip and off-chip components.
摘要翻译： 提供的方法和装置用于通过各种总线，结构和输入/输出线将片上组件（例如可编程芯片上的组件）与片外组件相互连接。 诸如输入/输出线之类的互连资源被共享以与诸如存储器之类的不同的片外组件进行通信。 提供控制电路和仲裁结构以进一步提高片上和片外组件之间的通信效率。
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3.发明授权Scheduling logic on a programmable device implemented using a high-level language 有权使用高级语言实现的可编程设备上的调度逻辑公开(公告)号：US07409670B1
公开(公告)日：2008-08-05
申请号：US10993572
申请日：2004-11-16
申请人： J. Orion Pritchard , Todd Wayne
发明人： J. Orion Pritchard , Todd Wayne
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Methods and apparatus are provided for implementing a programmable device including a processor core, a hardware accelerator, and secondary components such as memory. A portion of a program written in a high-level language is automatically selected for hardware acceleration. Dedicated ports are generated to allow the hardware accelerator to handle pointer referencing and dereferencing. A hardware accelerator is generated to perform pipelined processing of instructions. The number of stages implemented for pipelined processing is at least partially dependent on the latency associated with accessing secondary components.
摘要翻译： 提供了用于实现包括处理器核心，硬件加速器和诸如存储器的次要组件的可编程设备的方法和装置。 自动选择以高级语言编写的程序的一部分用于硬件加速。 生成专用端口以允许硬件加速器处理指针引用和取消引用。 生成硬件加速器来执行指令的流水线处理。 流水线处理实现的阶段数至少部分取决于与访问次要组件相关的延迟。
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公开(公告)号：US6054704A
公开(公告)日：2000-04-25
申请号：US108110
申请日：1998-06-30
CPC分类号： H04N3/155
摘要： A storage pixel sensor comprises a photosensor selectively connectable to a reset potential; a switched buffer amplifier having a control terminal coupled to said photosensor, a first terminal connected to a source of a transfer signal, and a second terminal; a storage capacitor coupled to said second terminal of said switched buffer amplifier; and an amplifier coupled to said storage capacitor.
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公开(公告)号：US07533362B1
公开(公告)日：2009-05-12
申请号：US11385126
申请日：2006-03-20
申请人： J. Orion Pritchard
发明人： J. Orion Pritchard
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences or subroutines provided in a high-level language are overloaded with information to specify the number of hardware resources such as logic elements or functional blocks used to implement the code on a programmable chip. Code sequences remain compliant with standard high-level language compilers while also being able to provide resource count information to high-level language to hardware compilers.
摘要翻译： 提供了使用高级语言来实现可编程芯片的方法和装置。 以高级语言提供的代码序列或子程序由信息过载，以指定用于在可编程芯片上实现代码的逻辑元件或功能块等硬件资源的数量。 代码序列仍然符合标准的高级语言编译器，同时还能够向硬件编译器提供高级语言的资源计数信息。
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公开(公告)号：US06636261B1
公开(公告)日：2003-10-21
申请号：US09493855
申请日：2000-01-28
IPC分类号： H04N5335
CPC分类号： H04N5/37452
摘要： A storage pixel sensor comprises a photosensor selectively connectable to a reset potential; a switched buffer amplifier having a control terminal coupled to said photosensor, a first terminal connected to a source of a transfer signal, and a second terminal; a storage capacitor coupled to said second terminal of said switched buffer amplifier; and an amplifier coupled to said storage capacitor.
摘要翻译： 存储像素传感器包括可选择性地连接到复位电位的光传感器; 开关缓冲放大器，其具有耦合到所述光传感器的控制端子，连接到传送信号源的第一端子和第二端子; 耦合到所述开关缓冲放大器的所述第二端的存储电容器; 以及耦合到所述存储电容器的放大器。
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