公开(公告)号：US20100115385A1

公开(公告)日：2010-05-06

申请号：US12613399

申请日：2009-11-05

Applicant: NAVEEN BATRA ,  JITENDRA DASANI

Inventor： NAVEEN BATRA ,  JITENDRA DASANI

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/0727 ,  G06F11/0772 ,  G11C29/02 ,  G11C29/024 ,  G11C2029/0409

Abstract: An embodiment of the present disclosure relates to detection of data access element selection errors during data access in data storage arrays. An embodiment of the disclosure describes a system including a data storage array comprising a first and a second error identifier. The error identifiers generate an error signal in case multiple data access elements are selected or no data access element is selected, respectively. A system for detection of data-access-element-selection errors further comprises a common error-signal generator which provides an output when an error signal is generated by either of said error identifiers.

Abstract translation: 本公开的实施例涉及在数据存储阵列中的数据访问期间检测数据访问元素选择错误。 本公开的实施例描述了包括包括第一和第二错误标识符的数据存储阵列的系统。 在选择多个数据访问元素或没有选择数据访问元素的情况下，错误标识符生成错误信号。 用于检测数据访问元件选择错误的系统还包括公共误差信号发生器，当由所述错误标识符中的任一个生成错误信号时，该误差信号发生器提供输出。

公开(公告)号：US08526209B2

公开(公告)日：2013-09-03

申请号：US13168609

申请日：2011-06-24

Applicant: Jitendra Dasani

Inventor： Jitendra Dasani

IPC: G11C17/00

CPC classification number: G11C17/08 ,  G11C7/065 ,  G11C17/12 ,  H01L27/11226

Abstract: A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.

Abstract translation: 互补型只读存储器（ROM）单元包括晶体管; 以及与晶体管相邻的位线和互补位线; 其中所述晶体管的漏极端子基于所述ROM单元中编程的数据连接到所述位线和所述互补位线之一。

公开(公告)号：US20070201270A1

公开(公告)日：2007-08-30

申请号：US11648155

申请日：2006-12-29

Applicant: Kallol Chatterjee ,  Vivek Asthana ,  Jitendra Dasani

Inventor： Kallol Chatterjee ,  Vivek Asthana ,  Jitendra Dasani

IPC: G11C16/04

CPC classification number: G11C17/10

Abstract: A memory chip configuration aims that reduces the bitline leakage in standby as well as dynamic operation mode. The chip design comprises of—a n×m FET matrix, vertically running bitlines—each shared by a column in the array, horizontally running wordlines—each shared by a row in the array, horizontally running sourcelines—each shared by a row in the array. The sourceline signal for a row is generated by complementing the wordline signal for the same row. The memory cell read operations with the proposed configuration, substantially control the bitline leakage current thereby enhancing the memory speed by reducing the noise during read operations. Also the configuration is unconstrained by design parameters that include size and geometries of memory chips, cell densities, complexity of memory structures, fabrication technologies, etc.

Abstract translation: 存储器芯片配置旨在减少待机和动态操作模式下的位线泄漏。 芯片设计包括一个nxm FET矩阵，垂直运行的位线，每个位线由数组中的一个列共享，每个数组水平运行的字线，每个字段由数组中的一个行共享，水平运行源线，每个数组都由数组中的一行共享。 通过对同一行的字线信号进行补码来生成行的源极线信号。 利用所提出的配置，存储单元读取操作，基本上控制位线泄漏电流，从而通过降低读取操作期间的噪声来增强存储器速度。 此外，该配置不受包括存储器芯片的尺寸和几何形状，单元密度，存储器结构的复杂性，制造技术等的设计参数的约束。

公开(公告)号：US08378711B2

公开(公告)日：2013-02-19

申请号：US13038236

申请日：2011-03-01

Applicant: Chirag Gulati ,  Jitendra Dasani ,  Rita Zappa ,  Stefano Corbani

Inventor： Chirag Gulati ,  Jitendra Dasani ,  Rita Zappa ,  Stefano Corbani

IPC: H03K19/003

CPC classification number: H03K19/007

Abstract: A circuit for detecting a single bit upset in a dynamic logic circuit includes a latch circuit having an input for receiving a reset signal, and an output for providing a flag output signal, the latch circuit being clocked by a first clock signal, a first transistor having a drain coupled to the output of the latch circuit, a gate for receiving a second clock signal, and a source, and a second transistor having a drain coupled to the source of the first transistor, a gate for receiving a third clock signal, and a source coupled to ground.

Abstract translation: 一种用于检测动态逻辑电路中的单位置位的电路包括具有用于接收复位信号的输入端的锁存电路和用于提供标志输出信号的输出，所述锁存电路由第一时钟信号计时，第一晶体管 具有耦合到锁存电路的输出的漏极，用于接收第二时钟信号的栅极和源极以及耦合到第一晶体管的源极的漏极的第二晶体管，用于接收第三时钟信号的栅极， 以及耦合到地面的源。

公开(公告)号：US20120163063A1

公开(公告)日：2012-06-28

申请号：US13168609

申请日：2011-06-24

Applicant: Jitendra DASANI

Inventor： Jitendra DASANI

IPC: G11C17/08 ,  H01L21/8246

CPC classification number: G11C17/08 ,  G11C7/065 ,  G11C17/12 ,  H01L27/11226

Abstract: A complementary read-only memory (ROM) cell includes a transistor; and a bit line and a complementary bit line adjacent to the transistor; wherein a drain terminal of the transistor is connected to one of the bit line and the complementary bit line based on data programmed in the ROM cell.

Abstract translation: 互补型只读存储器（ROM）单元包括晶体管; 以及与晶体管相邻的位线和互补位线; 其中所述晶体管的漏极端子基于所述ROM单元中编程的数据连接到所述位线和所述互补位线之一。

公开(公告)号：US20120223735A1

公开(公告)日：2012-09-06

申请号：US13038236

申请日：2011-03-01

Applicant: Chirag GULATI ,  Jitendra DASANI ,  Rita ZAPPA ,  Stefano CORBANI

Inventor： Chirag GULATI ,  Jitendra DASANI ,  Rita ZAPPA ,  Stefano CORBANI

IPC: H03K19/003

CPC classification number: H03K19/007

Abstract: A circuit for detecting a single bit upset in a dynamic logic circuit includes a latch circuit having an input for receiving a reset signal, and an output for providing a flag output signal, the latch circuit being clocked by a first clock signal, a first transistor having a drain coupled to the output of the latch circuit, a gate for receiving a second clock signal, and a source, and a second transistor having a drain coupled to the source of the first transistor, a gate for receiving a third clock signal, and a source coupled to ground.

Abstract translation: 一种用于检测动态逻辑电路中的单位置位的电路包括具有用于接收复位信号的输入端的锁存电路和用于提供标志输出信号的输出，所述锁存电路由第一时钟信号计时，第一晶体管 具有耦合到锁存电路的输出的漏极，用于接收第二时钟信号的栅极和源极以及耦合到第一晶体管的源极的漏极的第二晶体管，用于接收第三时钟信号的栅极， 以及耦合到地面的源。