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    APPARATUS FOR RECOGNIZING AND PROCESSING INFORMATION OF ELECTRONIC PARTS
    1.
    发明申请
    APPARATUS FOR RECOGNIZING AND PROCESSING INFORMATION OF ELECTRONIC PARTS 有权
    电子部件识别和处理信息的设备

    公开(公告)号：US20100070067A1

    公开(公告)日：2010-03-18

    申请号：US12557742

    申请日：2009-09-11

    申请人： Ja-Hyun Koo ,  Man-Hee Lee ,  Sun-Jeong Kang

    发明人： Ja-Hyun Koo ,  Man-Hee Lee ,  Sun-Jeong Kang

    IPC分类号： G06F17/00 ,  G05D3/12 ,  G06T7/00

    CPC分类号： H05K13/0812 ,  H05K13/0813 ,  Y10T29/49131 ,  Y10T29/49155 ,  Y10T29/49208 ,  Y10T29/49547

    摘要： An apparatus for recognizing and processing information of electronic parts includes a seating unit on which electronic parts are seated and aligned and a part information processing unit disposed adjacent to the seating unit. The part information processing unit is configured to align the electronic parts using the seating unit, recognize a recognition surface of the electronic parts, obtaining part information of the recognized surface, and store the obtained part information.

    摘要翻译： 一种用于识别和处理电子部件的信息的装置包括：座位单元，电子部件位于其上并对齐;以及零件信息处理单元，邻近座位单元设置。 部件信息处理单元被配置为使用座位单元对准电子部件，识别电子部件的识别表面，获得识别表面的部分信息，并存储所获得的部件信息。

    Test method for high speed memory devices in which limit conditions for the clock are defined
    3.
    发明授权
    Test method for high speed memory devices in which limit conditions for the clock are defined 失效
    定义时钟限制条件的高速存储器件的测试方法

    公开(公告)号：US06201746B1

    公开(公告)日：2001-03-13

    申请号：US09107947

    申请日：1998-06-30

    申请人： Ja-hyun Koo ,  Jong-bok Tcho ,  Hyun-seop Shim ,  Jeong-ho Bang

    发明人： Ja-hyun Koo ,  Jong-bok Tcho ,  Hyun-seop Shim ,  Jeong-ho Bang

    IPC分类号： G11C700

    CPC分类号： G11C29/14

    摘要： When high speed memory devices are tested using a tester having a lower operating frequency than the operational speed of the memory device, limit conditions for the tester signals are required to prevent the interference between the tester and device signals. The present invention provides the limit conditions for the shift and strobe signal. The strobe signal is delivered to comparators with a delivery delay time defining the dead time zone. The shift signal controls the data path of the device to and from a driver and a comparator. When the strobe signal is within the present test cycle, the shift signal of a read cycle must be activated at the same time or earlier than the activation time of the WE/ signal of the next write cycle and the shift signal of a write cycle must start at the same time or earlier than the activation time of the OE/ signal of the next read cycle. When the strobe signal is outside of the test cycle, the shift signal must meet prescribed maximum and minimum timing conditions.

    摘要翻译： 当使用具有比存储器件的操作速度更低的工作频率的测试仪测试高速存储器件时，需要测试仪信号的限制条件以防止测试仪和器件信号之间的干扰。 本发明提供了移位和选通信号的限制条件。 选通信号通过定义死区时间的传送延迟时间传送给比较器。 移位信号控制设备到驱动器和比较器的数据路径。 当选通信号在当前测试周期内时，读周期的移位信号必须与下一个写周期的WE /信号的激活时间相同或早于激活时间，并且写周期的移位信号必须 同时或早于下一个读取周期的OE /信号的激活时间启动。 当选通信号超出测试周期时，移位信号必须满足规定的最大和最小定时条件。