公开(公告)号：US06408077B1

公开(公告)日：2002-06-18

申请号：US09018206

申请日：1998-02-03

申请人： Jacques Prunier

发明人： Jacques Prunier

IPC分类号： H04L900

CPC分类号： G06F21/77 ,  G06F5/06 ,  H04N7/163

摘要： In a device for descrambling scrambled digital data, the digital data are grouped into parallel combinations of bits before being descrambled. The combinations of bits are descrambled and then split back into a serial stream of bits.

摘要翻译： 在用于对加扰数字数据进行解扰的装置中，数字数据在被解扰之前被分组成并行的比特组合。 比特的组合被解扰，然后分解成串行的比特流。

公开(公告)号：US5944835A

公开(公告)日：1999-08-31

申请号：US863320

申请日：1997-05-27

申请人： Laurent Lusinchi ,  Jacques Prunier

发明人： Laurent Lusinchi ,  Jacques Prunier

IPC分类号： G06F1/025 ,  G06F1/08

CPC分类号： G06F1/025

摘要： The present invention relates to a method for generating pulses using a microprocessor including a CPU and a counter programmable by at least one control bit and of a counting threshold, consisting of generating a first edge of a pulse by unconditionally forcing the state of an output signal of the counter to a state corresponding to a state of the control bit, and generating a second edge of the pulse by switching the state of the output signal at the end of the counting threshold.

摘要翻译： 本发明涉及一种使用微处理器产生脉冲的方法，所述微处理器包括CPU和通过至少一个控制位可编程的计数器和计数阈值，其包括通过无条件地强制输出信号的状态产生脉冲的第一边缘 所述计数器与对应于所述控制位的状态的状态相对应，并且通过在所述计数阈值结束时切换所述输出信号的状态来产生所述脉冲的第二边沿。

公开(公告)号：US06938194B2

公开(公告)日：2005-08-30

申请号：US10083714

申请日：2002-02-26

申请人： Jacques Prunier

发明人： Jacques Prunier

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318555 ,  G01R31/318552

摘要： A system for testing an integrated circuit, the integrated circuit including: flip-flops connected to a logic block and the test system including circuitry for connecting the flip-flops as a register, circuitry for inhibiting the different elements of the logic block capable of disturbing the sequencing of the register or the propagation of the signals into the logic block, and a control circuit for separately controlling the different inhibiting circuits and the circuitry for connecting the flip-flops as a register.

摘要翻译： 一种用于测试集成电路的系统，该集成电路包括：连接到逻辑块的触发器和包括用于将触发器作为寄存器连接的电路的测试系统，用于抑制能够干扰的逻辑块的不同元件的电路 寄存器的顺序或信号传播到逻辑块中的控制电路，以及用于分别控制不同抑制电路的控制电路和用于将触发器作为寄存器连接的电路。

公开(公告)号：US06321354B1

公开(公告)日：2001-11-20

申请号：US09067893

申请日：1998-04-28

申请人： Jacques Prunier

发明人： Jacques Prunier

IPC分类号： G01R3128

CPC分类号： G06F11/2236

摘要： The present invention relates to an electronic device of the “SMARTCARD” type including a single input/output lead for communicating with the microcontroller from the outside. Interface registers between a peripheral and the microcontroller are likely to be connected according to a shift register configuration forming a test scan path accessible in series and clocked by a clock signal to be applied to a peripheral clock lead. A test aid circuit, in a scan mode, connects the interface registers according to the shift register configuration, the scan mode being selected when a test bit, accessible through the input/output lead, is enabled and the input/output lead is forced from the outside to a state distinct from its default state.

摘要翻译： 本发明涉及“智能卡”类型的电子设备，包括用于从外部与微控制器进行通信的单个输入/输出引线。 外围设备和微控制器之间的接口寄存器很可能根据移位寄存器配置进行连接，形成一个串行可访问的测试扫描路径，并由一个要施加到外围时钟引线的时钟信号计时。 在扫描模式下的测试辅助电路根据移位寄存器配置连接接口寄存器，当通过输入/输出引线可访问的测试位被激活时，选择扫描模式，并且强制输入/输出引线 外部状态与其默认状态不同。

公开(公告)号：US5870593A

公开(公告)日：1999-02-09

申请号：US861357

申请日：1997-05-21

申请人： Jacques Prunier ,  Laurent Lusinchi

发明人： Jacques Prunier ,  Laurent Lusinchi

IPC分类号： H04B10/114 ,  H04L27/04 ,  G06F1/04

CPC分类号： H04B10/1141 ,  H04L27/04

摘要： The present invention relates to a method for generating pulse trains by means of a microprocessor, consisting of generating an envelope signal by means of a timer which is programmable by a CPU, the width of a square wave of the envelope signal corresponding to the width of the pulse trains, generating a carrier signal having a predetermined frequency, and modulating the envelope signal with the carrier.

摘要翻译： 本发明涉及一种通过微处理器生成脉冲串的方法，包括通过可由CPU编程的定时器产生包络信号，包络信号的方波宽度对应于 脉冲串，产生具有预定频率的载波信号，并用载波调制包络信号。