公开(公告)号：US07332750B1

公开(公告)日：2008-02-19

申请号：US09654845

申请日：2000-09-01

申请人： Jifa Hao ,  John L. Benjamin ,  Randall L. Case ,  Jae J. Yun

发明人： Jifa Hao ,  John L. Benjamin ,  Randall L. Case ,  Jae J. Yun

IPC分类号： H01L29/74 ,  H01L29/30

CPC分类号： H01L29/0615 ,  H01L29/7395 ,  H01L29/8611

摘要： A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N− doped, P− doped, and P+ doped semiconductor layers, the P− and P+ doped layers having a combined thickness of about 5 μm to about 12 μm. Recombination centers comprising noble metal impurities are disposed substantially in the N− and P− doped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an N− doped epitaxial layer on an N+ doped substrate, forming a P− doped layer in the N− doped epitaxial layer, forming a P+ doped layer in the P− doped layer, and forming in the P− and N− doped layers recombination centers comprising noble metal impurities. The P+ and P− doped layers have a combined thickness of about 5 μm to about 12 μm.

摘要翻译： 具有高雪崩能力的功率半导体器件包括掺杂N +的衬底，并且依次掺杂N掺杂的P掺杂的P和 掺杂半导体层的掺杂P +和/或P +掺杂层具有约5μm至约12μm的组合厚度。 包含贵金属杂质的复合中心基本上设置在N +和P + - SUP掺杂层中。 用于形成具有高雪崩能力的功率半导体器件的工艺包括：在掺杂N +的衬底上形成掺杂N +的外延层，形成P + / SUP>掺杂层，在掺杂P的掺杂层中形成掺杂P +的掺杂层，并形成 包含贵金属杂质的掺杂层和复合掺杂层复合中心。 掺杂P +的掺杂层具有约5μm至约12μm的组合厚度。