公开(公告)号：US08492837B2

公开(公告)日：2013-07-23

申请号：US13283496

申请日：2011-10-27

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Thomas E. Grebs ,  John L. Benjamin

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Thomas E. Grebs ,  John L. Benjamin

IPC分类号： H01L29/872

CPC分类号： H01L29/407 ,  H01L29/36 ,  H01L29/8725

摘要： Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.

摘要翻译： 公开了制造半导体器件的半导体器件和方法。 示例性实施例包括第一导电类型的半导体层，其具有在半导体层的一部分内的第一导电类型的第一表面，第二表面和渐变网掺杂浓度。 分级部分位于与半导体层的顶表面相邻的位置，并且其中的渐变网络掺杂浓度随距离半导体层的顶表面的距离而减小。 示例性器件还包括设置在半导体层的第一表面并且与渐变部分相邻的电极。

公开(公告)号：US20120037982A1

公开(公告)日：2012-02-16

申请号：US13283496

申请日：2011-10-27

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Thomas E. Grebs ,  John L. Benjamin

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Thomas E. Grebs ,  John L. Benjamin

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/407 ,  H01L29/36 ,  H01L29/8725

摘要： Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.

摘要翻译： 公开了制造半导体器件的半导体器件和方法。 示例性实施例包括第一导电类型的半导体层，其具有在半导体层的一部分内的第一导电类型的第一表面，第二表面和等级净掺杂浓度。 分级部分位于与半导体层的顶表面相邻的位置，并且其中的渐变网络掺杂浓度随距离半导体层的顶表面的距离而减小。 示例性器件还包括设置在半导体层的第一表面并且与渐变部分相邻的电极。

公开(公告)号：US08049276B2

公开(公告)日：2011-11-01

申请号：US12484096

申请日：2009-06-12

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Thomas E. Grebs ,  John L. Benjamin

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Thomas E. Grebs ,  John L. Benjamin

IPC分类号： H01L29/66

CPC分类号： H01L29/407 ,  H01L29/36 ,  H01L29/8725

摘要： Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.

摘要翻译： 公开了制造半导体器件的半导体器件和方法。 示例性实施例包括第一导电类型的半导体层，其具有在半导体层的一部分内的第一导电类型的第一表面，第二表面和等级净掺杂浓度。 分级部分位于与半导体层的顶表面相邻的位置，并且其中的渐变网络掺杂浓度随距离半导体层的顶表面的距离而减小。 示例性器件还包括设置在半导体层的第一表面并且与渐变部分相邻的电极。

公开(公告)号：US20080210974A1

公开(公告)日：2008-09-04

申请号：US11972908

申请日：2008-01-11

申请人： Jifa Hao ,  John L. Benjamin ,  Randall L. Case ,  Joe L. Yun

发明人： Jifa Hao ,  John L. Benjamin ,  Randall L. Case ,  Joe L. Yun

IPC分类号： H01L29/739 ,  H01L29/78

CPC分类号： H01L29/0615 ,  H01L29/7395 ,  H01L29/8611

摘要： A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N− doped, P− doped, and P+ doped semiconductor layers, the P− and P+ doped layers having a combined thickness of about 5 μm to about 12 μm. Recombination centers comprising noble metal impurities are disposed substantially in the N− and P− doped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an N− doped epitaxial layer on an N+ doped substrate, forming a P− doped layer in the N− doped epitaxial layer, forming a P+ doped layer in the P− doped layer, and forming in the P− and N− doped layers recombination centers comprising noble metal impurities. The P+ and P−doped layers have a combined thickness of about 5 μm to about 12 μm.

摘要翻译： 具有高雪崩能力的功率半导体器件包括掺杂N +的衬底，并且依次掺杂N掺杂的P掺杂的P和 掺杂半导体层的掺杂P +和/或P +掺杂层具有约5μm至约12μm的组合厚度。 包含贵金属杂质的复合中心基本上设置在N +和P + - SUP掺杂层中。 用于形成具有高雪崩能力的功率半导体器件的工艺包括：在掺杂N +的衬底上形成掺杂N +的外延层，形成P + / SUP>掺杂层，在掺杂P的掺杂层中形成掺杂P +的掺杂层，并形成 包含贵金属杂质的掺杂层和复合掺杂层复合中心。 掺杂P +的掺杂层具有约5μm至约12μm的组合厚度。

公开(公告)号：US06465325B2

公开(公告)日：2002-10-15

申请号：US10082944

申请日：2002-02-26

申请人： Rodney S. Ridley ,  Frank Stensney ,  John L. Benjamin ,  Jack H. Linn

发明人： Rodney S. Ridley ,  Frank Stensney ,  John L. Benjamin ,  Jack H. Linn

IPC分类号： H01L2176

CPC分类号： H01L29/7813 ,  H01L21/76224 ,  H01L21/763 ,  H01L29/4236

摘要： A process for filling a trench having sidewalls and a floor in a semiconductor device or integrated circuit comprises: forming an insulating layer on the sidewalls and floor of a trench in a semiconductor substrate, substantially filling the trench with semiconductor material, removing semiconductor material from an upper portion of the trench, depositing a first layer of BPSG in the upper portion of the trench, heating the substrate to a first temperature greater than about 850° C. and up to about 1100° C., depositing a second layer of BPSG above the first layer of BPSG, and heating the substrate to a second temperature greater than about 850° C. and up to about 1100° C. The first and second BPSG layers each comprises boron and phosphorus in a weight ratio of boron: phosphorus of greater than 1:1.

摘要翻译： 一种用于在半导体器件或集成电路中填充具有侧壁和地板的沟槽的工艺包括：在半导体衬底的沟槽的侧壁和底板上形成绝缘层，基本上用半导体材料填充沟槽，从半导体材料中去除半导体材料 在沟槽的上部沉积第一层BPSG，将衬底加热至高于约850℃和高达约1100℃的第一温度，将第二层BPSG沉积在上述 第一层BPSG，并将衬底加热到​​大于约850℃和高达约1100℃的第二温度。第一和第二BPSG层各自包含硼：磷的重量比为更大的硼和磷 超过1：1。

公开(公告)号：US4597822A

公开(公告)日：1986-07-01

申请号：US717364

申请日：1985-03-28

申请人： John L. Benjamin ,  William R. Van Dell

发明人： John L. Benjamin ,  William R. Van Dell

IPC分类号： H01L21/322 ,  C30B25/18

CPC分类号： H01L21/3221

摘要： A method for manufacturing a silicon wafer includes growing a layer of low-resistivity crystalline silicon upon a precision-ground slice of single-crystal, high-resistivity silicon. The slice of single-crystal silicon has a thickness sufficient to withstand handling during the initial part of the processing. The crystalline silicon is built up to a thickness which is sufficient to withstand handling and processing of the finished wafer. The layer of single-crystal silicon is thereupon precision ground to reduce its final thickness to a value required for the devices to be formed thereon. The crystalline layer performs gettering to remove impurities from the single-crystal silicon during normal heating attendant to the formation of the solid-state devices thereon. The present invention further includes a silicon wafer made by the process of the invention.

摘要翻译： 制造硅晶片的方法包括在单晶高电阻率硅的精密接地片上生长低电阻率晶体硅层。 单晶硅切片具有足以承受处理初始部分处理的厚度。 结晶硅的厚度足以承受成品晶片的处理和加工。 因此，单晶硅层被精密研磨以将其最终厚度减小到在其上形成器件所需的值。 结晶层在正常加热期间进行吸杂以除去单晶硅中的杂质，伴随其上形成固态器件。 本发明还包括通过本发明的方法制造的硅晶片。

公开(公告)号：US20100314707A1

公开(公告)日：2010-12-16

申请号：US12484096

申请日：2009-06-12

申请人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Thomas E. Grebs ,  John L. Benjamin

发明人： Joseph A. Yedinak ,  Mark L. Rinehimer ,  Thomas E. Grebs ,  John L. Benjamin

IPC分类号： H01L29/872 ,  H01L21/22 ,  H01L21/33

CPC分类号： H01L29/407 ,  H01L29/36 ,  H01L29/8725

摘要： Disclosed are semiconductor devices and methods of making semiconductor devices. An exemplary embodiment comprises a semiconductor layer of a first conductivity type having a first surface, a second surface, and a graded net doping concentration of the first conductivity type within a portion of the semiconductor layer. The graded portion is located adjacent to the top surface of the semiconductor layer, and the graded net doping concentration therein decreasing in value with distance from the top surface of the semiconductor layer. The exemplary device also comprises an electrode disposed at the first surface of the semiconductor layer and adjacent to the graded portion.

摘要翻译： 公开了制造半导体器件的半导体器件和方法。 示例性实施例包括第一导电类型的半导体层，其具有在半导体层的一部分内的第一导电类型的第一表面，第二表面和等级净掺杂浓度。 分级部分位于与半导体层的顶表面相邻的位置，并且其中的渐变网络掺杂浓度随距离半导体层的顶表面的距离而减小。 示例性器件还包括设置在半导体层的第一表面并且与渐变部分相邻的电极。

公开(公告)号：US07332750B1

公开(公告)日：2008-02-19

申请号：US09654845

申请日：2000-09-01

申请人： Jifa Hao ,  John L. Benjamin ,  Randall L. Case ,  Jae J. Yun

发明人： Jifa Hao ,  John L. Benjamin ,  Randall L. Case ,  Jae J. Yun

IPC分类号： H01L29/74 ,  H01L29/30

CPC分类号： H01L29/0615 ,  H01L29/7395 ,  H01L29/8611

摘要： A power semiconductor device having high avalanche capability comprises an N+ doped substrate and, in sequence, N− doped, P− doped, and P+ doped semiconductor layers, the P− and P+ doped layers having a combined thickness of about 5 μm to about 12 μm. Recombination centers comprising noble metal impurities are disposed substantially in the N− and P− doped layers. A process for forming a power semiconductor device with high avalanche capability comprises: forming an N− doped epitaxial layer on an N+ doped substrate, forming a P− doped layer in the N− doped epitaxial layer, forming a P+ doped layer in the P− doped layer, and forming in the P− and N− doped layers recombination centers comprising noble metal impurities. The P+ and P− doped layers have a combined thickness of about 5 μm to about 12 μm.

摘要翻译： 具有高雪崩能力的功率半导体器件包括掺杂N +的衬底，并且依次掺杂N掺杂的P掺杂的P和 掺杂半导体层的掺杂P +和/或P +掺杂层具有约5μm至约12μm的组合厚度。 包含贵金属杂质的复合中心基本上设置在N +和P + - SUP掺杂层中。 用于形成具有高雪崩能力的功率半导体器件的工艺包括：在掺杂N +的衬底上形成掺杂N +的外延层，形成P + / SUP>掺杂层，在掺杂P的掺杂层中形成掺杂P +的掺杂层，并形成 包含贵金属杂质的掺杂层和复合掺杂层复合中心。 掺杂P +的掺杂层具有约5μm至约12μm的组合厚度。

公开(公告)号：US06358825B1

公开(公告)日：2002-03-19

申请号：US09718219

申请日：2000-11-21

申请人： Jifa Hao ,  Randall L. Case ,  John L. Benjamin

发明人： Jifa Hao ,  Randall L. Case ,  John L. Benjamin

IPC分类号： H01L2122

CPC分类号： H01L29/66128 ,  H01L29/868

摘要： In an improved process for controlling and improving minority carrier lifetime in a P-i-N diode, platinum is deposited on a surface of a silicon semiconductor substrate containing at least one PN junction. The substrate is heated to a temperature of about 800° C., and the platinum is diffused into the substrate as its temperature is increased at a rate of about 5° C./minute to a first selected temperature of about 850-950° C. Platinum diffusion is continued while the substrate is maintained at the first selected temperature for about 30-60 minutes. The substrate temperature is then increased at a rate of about 5° C./minute to a second selected temperature above 950° C. to about 1000° C., and the substrate is maintained at the second selected temperature for about 5-30 minutes before cooling.

摘要翻译： 在用于控制和改善P-i-N二极管中的少数载流子寿命的改进方法中，铂沉积在含有至少一个PN结的硅半导体衬底的表面上。 将基底加热到约800℃的温度，并且当铂以约5℃/分钟的速度升高至约850-950℃的第一选定温度时，铂扩散到基底中 铂基体继续扩散，同时将基底保持在第一选定温度约30-60分钟。 然后将衬底温度以约5℃/分钟的速率增加至高于950℃至约1000℃的第二选定温度，并将衬底保持在第二选定温度约5-30分钟 在冷却之前。

公开(公告)号：US4778776A

公开(公告)日：1988-10-18

申请号：US882857

申请日：1986-07-07

申请人： David W. Tong ,  John L. Benjamin ,  William R. VanDell

发明人： David W. Tong ,  John L. Benjamin ,  William R. VanDell

IPC分类号： H01L21/314 ,  H01L21/306 ,  B44C1/22

CPC分类号： H01L21/314 ,  Y10S257/905 ,  Y10S257/912

摘要： A process for depositing oxygen doped semi-insulating polycrystalline silicon (SIPOS) as a passivation layer over the junction of a semiconductor silicon substrate in which the substrate is subjected to an oxygen removal step immediately prior to the creation of the SIPOS layer to thereby prevent the creation of an oxide layer at the interface between the SIPOS and the substrate.

摘要翻译： 一种用于在半导体硅衬底的接合处的氧掺杂半绝缘多晶硅（SIPOS）上沉积氧化物半导体绝缘多晶硅（SIPOS）的工艺，其中衬底在创建SIPOS层之前立即进行除氧步骤，从而防止 在SIPOS和衬底之间的界面处形成氧化物层。