公开(公告)号：US06449755B1

公开(公告)日：2002-09-10

申请号：US09616388

申请日：2000-07-14

Applicant: James Beausang ,  Harbinder Singh

Inventor： James Beausang ,  Harbinder Singh

IPC: G06F1750

CPC classification number: G01R31/318591

Abstract: A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist. The TAP controller is extracted and its state ports are identified, referenced in a boundary scan design database (BSDD) and its states are verified. The TAP controller is controlled so that the instruction register is located and referenced in the BSDD. The TAP controller is controlled so that the bypass register is found and the BSDD is updated. The TAP controller is controlled so that the shift and update cells of the boundary scan register (BSR) are found, the control, input and output BSR cells are characterized and the BSDD is updated. Primary input and output information is also inferred and the device_ID register is found. Frontier pins are used to locate signatures of the remaining instructions and their test data registers are found. To infer the SAMPLE instruction, instructions selecting the BSR are groups and those that do not exhibit the behavior of the SAMPLE instruction are eliminated. Primary inputs and primary outputs are then inferred. The following instructions are then inferred: INTEST, HIGHZ, CLAMP, IDCODE and RUNBIST. As each of the above elements of the IEEE 1149.1 design are located, they are used to update the BSDD and are also inherently verified for compliance by the present invention. Intolerable violations flag a non-compliant design.

Abstract translation: 一种用于从网表自动提取IEEE 1149.1标准设计并执行合规性检查的计算机化方法和系统。 本发明接收网表的TAP（测试接入端口）描述和兼容性使能端口。 提取TAP控制器，其状态端口被识别，在边界扫描设计数据库（BSDD）中被引用，并且其状态被验证。 控制TAP控制器，使得指令寄存器位于BSDD中并被引用。 控制TAP控制器，以便找到旁路寄存器并更新BSDD。 控制TAP控制器，使得边界扫描寄存器（BSR）的移位和更新单元被发现，控制，输入和输出BSR单元被表征，BSDD被更新。 还推断了主输入和输出信息，并找到了device_ID寄存器。 前端引脚用于定位剩余指令的签名，并找到其测试数据寄存器。 为了推断SAMPLE指令，选择BSR的指令是组，并且没有表现出SAMPLE指令行为的指令被消除。 然后推断主输入和主输出。 然后推断以下说明：INTEST，HIGHZ，CLAMP，IDCODE和RUNBIST。 由于IEEE 1149.1设计的每个上述元件都位于其中，所以它们被用于更新BSDD，并且本身也被固有地验证了本发明的符合性。 不符合标准的违规设计。

公开(公告)号：US6106568A

公开(公告)日：2000-08-22

申请号：US324755

申请日：1999-06-03

Applicant: James Beausang ,  Chris Ellingham ,  Markus F. Robinson ,  Robert Walker

Inventor： James Beausang ,  Chris Ellingham ,  Markus F. Robinson ,  Robert Walker

IPC: G01R31/317 ,  G01R31/3185 ,  G06F17/50

CPC classification number: G01R31/318536 ,  G01R31/31704

Abstract: A system and method for architecting design for test circuitry (e.g., scan architecting) within an integrated circuit design having subdesigns (e.g., modules). The novel system contains a default operational mode (no user specification) and an operational mode based on user specifications; within either mode, the system recognizes and allows definition of subdesign scan chains which can be linked together alone or with other scan elements to architect complex scan chains (e.g., top level scan chains). The system includes specification, analysis, synthesis and reporting processes which can be used in an IC design having a hierarchical structure including modules. The specification process accesses a design database and a script file and allows a user to define global scan properties (scan style, number of chains, etc.), properties of a particular scan chain (membership, name, etc.), test signals (scan-in, scan-out, scan-enable, etc.), complex elements used as part of a scan chain without requiring scan replacement, wires and latches forming connections between scan elements; this information is associated with the selected design database. Analysis reads the design database and performs architecting of scan chains based on inferred scan elements of the design and defined (e.g. specified) scan elements. During analysis, the logic within the design database is not altered and a script is generated for user modification/verification. Specification and analysis can be executed iteratively until the desired scan structures are planned. Synthesis then implements the desired DFT circuitry by altering the design database based on the scan chains planned by analysis.

Abstract translation: 一种用于在具有子设计（例如，模块）的集成电路设计中对测试电路（例如，扫描架构）进行架构设计的系统和方法。 小说系统包含默认操作模式（无用户指定）和基于用户规格的操作模式; 在任一模式下，系统识别和允许定义可以单独或与其他扫描元件链接在一起以构建复杂扫描链（例如，顶级扫描链）的子设计扫描链。 该系统包括可用于具有包括模块的分层结构的IC设计中的规范，分析，综合和报告过程。 规范过程访问设计数据库和脚本文件，并允许用户定义全局扫描属性（扫描样式，链数等），特定扫描链的属性（成员资格，名称等），测试信号（ 扫描，扫描，扫描使能等），用作扫描链的一部分而不需要扫描替换的复杂元件，形成扫描元件之间的连接的电线和锁存器; 该信息与所选择的设计数据库相关联。 分析读取设计数据库，并基于设计和定义（例如指定的）扫描元素的推断的扫描元素执行扫描链的架构。 在分析期间，设计数据库中的逻辑不会被更改，并且为用户修改/验证生成脚本。 可以迭代执行规范和分析，直到计划所需的扫描结构。 然后，合成通过基于通过分析计划的扫描链改变设计数据库来实现期望的DFT电路。

公开(公告)号：US5696771A

公开(公告)日：1997-12-09

申请号：US649788

申请日：1996-05-17

Applicant: James Beausang ,  Kenneth Wagner ,  Robert Walker

Inventor： James Beausang ,  Kenneth Wagner ,  Robert Walker

IPC: G01R31/3185 ,  G01R31/28

CPC classification number: G01R31/318586

Abstract: A computer implemented process and system for effectively determining a set of sequential cells with a integrated circuit design that can be scan replaced (e.g. for design for test applications) to offer significant testability while still maintaining specified optimization (e.g., area and/or timing) constraints that are applicable to the design. The novel system selects sequential cells for scan replacement that offer best testability contribution while not selecting sequential cells for scan replacement that do not offer much testability contribution and/or are part of most critical paths within the design. The novel system is composed of a subtractive method and an additive method. The subtractive method inputs a fully scan replaced netlist (e.g., the sequential cells are scan replaced) that does not meet determined optimization constraints. The novel subtractive system unscans selected cells until the area and/or timing constraints are met. A flag indicates whether nor not timing is considered. Selection for unscanning is based on a testability cell list (TCL) that ranks cells by their degree of testability contribution; those cells with low degrees of testability are unscanned first. The additive process receives an unscanned netlist (original design) and scan replaces cells, using the TCL ranked list until optimization (e.g., area and/or timing) constraints of the design are violated. A flag indicates whether nor not timing is considered. The additive system iterates through the TCL list with the cells offering the most contribution for testability scan replaced first.

Abstract translation: 一种计算机实现的过程和系统，用于通过集成电路设计来有效地确定一组顺序单元，该集成电路设计可以被扫描替换（例如，用于测试应用的设计）以提供显着的可测试性，同时仍然保持指定的优化（例如，面积和/或定时） 适用于设计的约束。 该新颖系统选择用于扫描替换的顺序单元，其提供最佳可测性贡献，而不选择不提供很多可测性贡献的扫描替换的顺序单元和/或是设计中最关键路径的一部分。 该系统由减法法和加法法组成。 减法方法输入不满足确定的优化约束的完全扫描替换的网表（例如，顺序单元被扫描替换）。 新的减法系统扫描所选择的单元直到满足区域和/或时序约束。 一个标志指示是否考虑定时。 扫描的选择是基于可测试性细胞列表（TCL），其通过其可测性贡献程度来排列细胞; 那些具有低度可测性的电池首先是不可扫描的。 加法处理接收未扫描的网表（原始设计），并且使用TCL排名列表扫描替换单元，直到违反设计的优化（例如，区域和/或定时）约束。 一个标志指示是否考虑定时。 加法系统遍历TCL列表，首先替换为可测性扫描贡献最多的单元。

公开(公告)号：US6067650A

公开(公告)日：2000-05-23

申请号：US985614

申请日：1997-12-05

Applicant: James Beausang ,  Kenneth Wagner ,  Robert Walker

Inventor： James Beausang ,  Kenneth Wagner ,  Robert Walker

IPC: G01R31/3185 ,  G01R31/28

CPC classification number: G01R31/318586

Abstract: A computer implemented process and system for effectively determining a set of sequential cells with a integrated circuit design that can be scan replaced (e.g. for design for test applications) to offer significant testability while still maintaining specified optimization (e.g., area and/or timing) constraints that are applicable to the design. The novel system selects sequential cells for scan replacement that offer best testability contribution while not selecting sequential cells for scan replacement that do not offer much testability contribution and/or are part of most critical paths within the design. The novel system is composed of a subtractive method and an additive method. The subtractive method inputs a fully scan replaced netlist (e.g., the sequential cells are scan replaced) that does not meet determined optimization constraints. The novel subtractive system unscans selected cells until the area and/or timing constraints are met. A flag indicates whether nor not timing is considered. Selection for unscanning is based on a testability cell list (TCL) that ranks cells by their degree of testability contribution; those cells with low degrees of testability are unscanned first. The additive process receives an unscanned netlist (original design) and scan replaces cells, using the TCL ranked list until optimization (e.g., area and/or timing) constraints of the design are violated. A flag indicates whether nor not timing is considered. The additive system iterates through the TCL list with the cells offering the most contribution for testability scan replaced first.

Abstract translation: 一种计算机实现的过程和系统，用于通过集成电路设计来有效地确定一组顺序单元，该集成电路设计可以被扫描替换（例如，用于测试应用的设计）以提供显着的可测试性，同时仍然保持指定的优化（例如，面积和/或定时） 适用于设计的约束。 该新颖系统选择用于扫描替换的顺序单元，其提供最佳可测性贡献，而不选择不提供很多可测性贡献的扫描替换的顺序单元和/或是设计中最关键路径的一部分。 该系统由减法法和加法法组成。 减法方法输入不满足确定的优化约束的完全扫描替换的网表（例如，顺序单元被扫描替换）。 新的减法系统扫描所选择的单元直到满足区域和/或时序约束。 一个标志指示是否考虑定时。 扫描的选择是基于可测试性细胞列表（TCL），其通过其可测性贡献程度来排列细胞; 那些具有低度可测性的电池首先是不可扫描的。 加法处理接收未扫描的网表（原始设计），并且使用TCL排名列表扫描替换单元，直到违反设计的优化（例如，区域和/或定时）约束。 一个标志指示是否考虑定时。 加法系统遍历TCL列表，首先替换为可测性扫描贡献最多的单元。

公开(公告)号：US5949692A

公开(公告)日：1999-09-07

申请号：US704129

申请日：1996-08-28

Applicant: James Beausang ,  Chris Ellingham ,  Markus F. Robinson ,  Robert Walker

Inventor： James Beausang ,  Chris Ellingham ,  Markus F. Robinson ,  Robert Walker

IPC: G01R31/317 ,  G01R31/3185 ,  G06F17/50 ,  G01R31/28

CPC classification number: G01R31/318536 ,  G01R31/31704

Abstract: A system and method for architecting design for test circuitry (e.g., scan architecting) within an integrated circuit design having subdesigns (e.g., modules). The novel system contains a default operational mode (no user specification) and an operational mode based on user specifications; within either mode, the system recognizes and allows definition of subdesign scan chains which can be linked together alone or with other scan elements to architect complex scan chains (e.g., top level scan chains). The system includes specification, analysis, synthesis and reporting processes which can be used in an IC design having a hierarchical structure including modules. The specification process accesses a design database and a script file and allows a user to define global scan properties (scan style, number of chains, etc.), properties of a particular scan chain (membership, name, etc.), test signals (scan-in, scan-out, scan-enable, etc.), complex elements used as part of a scan chain without requiring scan replacement, wires and latches forming connections between scan elements; this information is associated with the selected design database. Analysis reads the design database and performs architecting of scan chains based on inferred scan elements of the design and defined (e.g. specified) scan elements. During analysis, the logic within the design database is not altered and a script is generated for user modification/verification. Specification and analysis can be executed iteratively until the desired scan structures are planned. Synthesis then implements the desired DFT circuitry by altering the design database based on the scan chains planned by analysis.

公开(公告)号：US5831868A

公开(公告)日：1998-11-03

申请号：US987868

申请日：1997-12-09

Applicant: James Beausang ,  Robert Walker

Inventor： James Beausang ,  Robert Walker

IPC: G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F17/50

CPC classification number: G01R31/318583 ,  G01R31/31716 ,  G01R31/318342 ,  G01R31/318364 ,  G01R31/318378 ,  G01R31/318536 ,  G01R31/318572

Abstract: A computer implemented process and system for providing a test ready (TR) compiler with specific information regarding the impact of added scannable cells and resources on its mission mode design. In so doing, the TR compiler optimizes more effectively for added test resources (e.g., scannable cells and other scan routing resources) so that predetermined performance and design related constraints of the mission mode design are maintained. The TR compiler translates generic sequential cells into technology dependent non-scan cells. In the TR compiler, during replacement, scannable memory cells are used in place of these non-scan memory cells specified within the mission mode circuitry. In this way, the TR compiler is informed of the characteristics of the scannable memory cells during optimization. For test, the scannable memory cells are chained to each other to form chain chains of sequential cells. To account for chaining during compile, the TR compiler provides output driven loopback connections to simulate electrical characteristics of the chain during compile. In the above implementation, the TR compiler can efficiently provide translation of an HDL description with test implementations into a gate level netlist. With the addition of certain information regarding the test implementation (e.g., scan replacement is done and loopback connections are added), the TR compiler of the present invention can better optimize the overall layout for the addition of the test resources.

Abstract translation: 一种计算机实现的过程和系统，用于向测试就绪（TR）编译器提供关于附加的可扫描单元和资源对其任务模式设计的影响的具体信息。 这样做，TR编译器可以更有效地优化添加的测试资源（例如，可扫描单元和其他扫描路由资源），以便维护任务模式设计的预定性能和设计相关约束。 TR编译器将通用顺序单元转换为依赖于技术的非扫描单元。 在TR编译器中，在替换期间，可以使用可扫描存储单元代替任务模式电路中指定的这些非扫描存储单元。 以这种方式，在优化过程中，向TR编译器通知可扫描存储单元的特性。 为了测试，可扫描的记忆细胞彼此链接以形成顺序细胞的链。 为了在编译期间考虑链接，TR编译器提供输出驱动的环回连接，以在编译期间模拟链的电气特性。 在上述实现中，TR编译器可以有效地将HDL描述与测试实现一起翻译成门级网表。 通过添加关于测试实现的某些信息（例如，扫描更换完成并且添加了环回连接），本发明的TR编译器可以更好地优化用于添加测试资源的总体布局。

公开(公告)号：US6141790A

公开(公告)日：2000-10-31

申请号：US960853

申请日：1997-10-30

Applicant: James Beausang ,  Harbinder Singh

Inventor： James Beausang ,  Harbinder Singh

IPC: G01R31/3185 ,  G06F17/50 ,  G01R31/303 ,  G01R31/3187

CPC classification number: G01R31/318591

Abstract: A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist. The TAP controller is extracted and its state ports are identified, referenced in a boundary scan design database (BSDD) and its states are verified. The TAP controller is controlled so that the instruction register is located and referenced in the BSDD. The TAP controller is controlled so that the bypass register is found and the BSDD is updated. The TAP controller is controlled so that the shift and update cells of the boundary scan register (BSR) are found, the control, input and output BSR cells are characterized and the BSDD is updated. Primary input and output information is also inferred and the device.sub.-- ID register is found. Frontier pins are used to locate signatures of the remaining instructions and their test data registers are found. To infer the SAMPLE instruction, instructions selecting the BSR are groups and those that do not exhibit the behavior of the SAMPLE instruction are eliminated. Primary inputs and primary outputs are then inferred. The following instructions are then inferred: INTEST, HIGHZ, CLAMP, IDCODE and RUNBIST. As each of the above elements of the IEEE 1149.1 design are located, they are used to update the BSDD and are also inherently verified for compliance by the present invention. Intolerable violations flag a non-compliant design.

Abstract translation: 一种用于从网表自动提取IEEE 1149.1标准设计并执行合规性检查的计算机化方法和系统。 本发明接收网表的TAP（测试接入端口）描述和兼容性使能端口。 提取TAP控制器，其状态端口被识别，在边界扫描设计数据库（BSDD）中被引用，并且其状态被验证。 控制TAP控制器，使得指令寄存器位于BSDD中并被引用。 控制TAP控制器，以便找到旁路寄存器并更新BSDD。 控制TAP控制器，使得边界扫描寄存器（BSR）的移位和更新单元被发现，控制，输入和输出BSR单元被表征，BSDD被更新。 还推断出主输入和输出信息，并找到设备ID寄存器。 前端引脚用于定位剩余指令的签名，并找到其测试数据寄存器。 为了推断SAMPLE指令，选择BSR的指令是组，并且没有表现出SAMPLE指令行为的指令被消除。 然后推断主输入和主输出。 然后推断以下说明：INTEST，HIGHZ，CLAMP，IDCODE和RUNBIST。 由于IEEE 1149.1设计的每个上述元件都位于其中，所以它们被用于更新BSDD，并且本身也被固有地验证了本发明的符合性。 不符合标准的违规设计。

公开(公告)号：US6012155A

公开(公告)日：2000-01-04

申请号：US961389

申请日：1997-10-30

Applicant: James Beausang ,  Harbinder Singh

Inventor： James Beausang ,  Harbinder Singh

IPC: G01R31/3185 ,  G06F7/24

CPC classification number: G01R31/318583

Abstract: A computerized method and system for automatically extracting an IEEE 1149.1 standard design from a netlist and performing compliance checking. The present invention receives the TAP (test access port) description and compliance enable ports of a netlist. The TAP controller is extracted and its state ports are identified, referenced in a boundary scan design database (BSDD) and its states are verified. The TAP controller is controlled so that the instruction register is located and referenced in the BSDD. The TAP controller is controlled so that the bypass register is found and the BSDD is updated. The TAP controller is controlled so that the shift and update cells of the boundary scan register (BSR) are found, the control, input and output BSR cells are characterized and the BSDD is updated. Primary input and output information is also inferred and the device.sub.-- ID register is found. Frontier pins are used to locate signatures of the remaining instructions and their test data registers are found. To infer the SAMPLE instruction, instructions selecting the BSR are groups and those that do not exhibit the behavior of the SAMPLE instruction are eliminated. Primary inputs and primary outputs are then inferred. The following instructions are then inferred: INTEST, HIGHZ, CLAMP, IDCODE and RUNBIST. As each of the above elements of the IEEE 1149.1 design are located, they are used to update the BSDD and are also inherently verified for compliance by the present invention. Intolerable violations flag a non-compliant design.

Abstract translation: 一种用于从网表自动提取IEEE 1149.1标准设计并执行合规性检查的计算机化方法和系统。 本发明接收网表的TAP（测试接入端口）描述和兼容性使能端口。 提取TAP控制器，其状态端口被识别，在边界扫描设计数据库（BSDD）中被引用，并且其状态被验证。 控制TAP控制器，使得指令寄存器位于BSDD中并被引用。 控制TAP控制器，以便找到旁路寄存器并更新BSDD。 控制TAP控制器，使得边界扫描寄存器（BSR）的移位和更新单元被发现，控制，输入和输出BSR单元被表征，BSDD被更新。 还推断出主输入和输出信息，并找到设备ID寄存器。 前端引脚用于定位剩余指令的签名，并找到其测试数据寄存器。 为了推断SAMPLE指令，选择BSR的指令是组，并且没有表现出SAMPLE指令行为的指令被消除。 然后推断主输入和主输出。 然后推断以下说明：INTEST，HIGHZ，CLAMP，IDCODE和RUNBIST。 由于IEEE 1149.1设计的每个上述元件都位于其中，所以它们被用于更新BSDD，并且本身也被固有地验证了本发明的符合性。 不符合标准的违规设计。

公开(公告)号：US5903466A

公开(公告)日：1999-05-11

申请号：US581379

申请日：1995-12-29

Applicant: James Beausang ,  Chris Ellingham ,  Robert Walker

Inventor： James Beausang ,  Chris Ellingham ,  Robert Walker

IPC: G01R31/317 ,  G01R31/3185 ,  G06F17/50 ,  G06F17/00

CPC classification number: G01R31/31704 ,  G01R31/31716 ,  G01R31/318586 ,  G06F17/5045 ,  G06F2217/14

Abstract: A computer implemented process and system for providing a scan insertion process having a reduced set of constraint driven compiler optimizations that provide an efficient and effective optimization for design for test implementations. The present invention includes a three tiered effort performance optimization process within a scan insertion process; a first tier operates to perform a set of optimizations (size design) only on elements of the design added for design for test (DFT). The second tier offers the first tier and performs the size design optimizations across all of the design while the third tier offers the second tier with sequential optimizations, circuit size downs, and another size design. Each higher user-selectable tier offers more complex optimizations and consumes additional processing time. An option to perform design constraints optimization (max fanout, max signal transition, and max capacitance) is also available. By utilizing a reduced set of performance optimizations, the present invention offers a post scan insertion compile technique that is fast enough to be practically used on chip level netlists. Hierarchical compilations for DFT are therefore allowed. Since the modified scan insertion procedure can operate in conjunction with a TR compiler of the present invention, the modified scan insertion procedure breaks loopback connections and generates proper scan chains. The scan insertion process of the present invention is compatible with netlists that contain a mixture of scan cells and non-scan cells.

Abstract translation: 一种计算机实现的过程和系统，用于提供扫描插入过程，该过程具有减少的约束驱动编译器优化集合，其为测试实现的设计提供有效且有效的优化。 本发明包括在扫描插入过程中的三层努力性能优化过程; 第一层仅针对为测试设计（DFT）添加的设计元素执行一组优化（尺寸设计）。 第二层提供第一层，并在所有设计中执行尺寸设计优化，而第三层则提供了具有顺序优化，电路尺寸下降和另一种尺寸设计的第二层。 每个较高的用户可选层提供更复杂的优化，并消耗额外的处理时间。 还可以选择执行设计约束优化（最大扇出，最大信号转换和最大电容）。 通过利用一组减少的性能优化，本发明提供了一种足够快速地在芯片级网表上实际使用的扫描后插入编译技术。 因此允许DFT的分层编译。 由于修改的扫描插入过程可以与本发明的TR编译器一起操作，所以修改的扫描插入过程中断环回连接并产生适当的扫描链。 本发明的扫描插入过程与包含扫描单元和非扫描单元的混合物的网表相兼容。

公开(公告)号：US5828579A

公开(公告)日：1998-10-27

申请号：US704152

申请日：1996-08-28

Applicant: James Beausang

Inventor： James Beausang

IPC: G01R31/317 ,  G01R31/3185 ,  G06F17/50

CPC classification number: G01R31/31704 ,  G01R31/318586

Abstract: A system and method for architecting design for test circuitry (e.g., scan architecting) within an integrated circuit design having subdesigns (e.g., modules). The novel system environment contains a default operational mode (no user specification) and an operational mode based on user specifications; within either mode, the system recognizes and allows definition of subdesign scan chains which can be linked together alone or with other scan elements to architect complex scan chains (e.g., top level scan chains). Individual scan chains are constructed using user defined scan segments and detected inferred segments. Inferred segments are automatically detected if present within IC module designs. When integrated into larger scan chains, the user defined scan segments and the inferred scan segments are not modified during linking. The system includes specification, analysis, synthesis and reporting processes which can be used in an IC design having a hierarchical structure including modules. The specification process accesses a design database and a script file and allows a user to define scan configuration information and scan chain specifications (e.g., set scan path commands) to define portions of scan chains. Analysis reads the design database and performs architecting of scan chains based on inferred scan elements of the design and defined (e.g. specified) scan elements. During analysis, the logic within the design database is not altered and a script is generated for user modification/verification. Synthesis then implements the desired DFT circuitry by altering the design database based on the scan chains planned by analysis.

Abstract translation: 一种用于在具有子设计（例如，模块）的集成电路设计中用于设计测试电路（例如，扫描架构）的系统和方法。 新颖的系统环境包含默认操作模式（无用户指定）和基于用户规格的操作模式; 在任一模式下，系统识别和允许定义可以单独或与其他扫描元件链接在一起以构建复杂扫描链（例如，顶级扫描链）的子设计扫描链。 使用用户定义的扫描段和检测到的推断段构建单个扫描链。 如果在IC模块设计中存在，则自动检测推断的段。 当集成到较大的扫描链中时，用户定义扫描段，并且在链接期间不会修改推断的扫描段。 该系统包括可用于具有包括模块的分层结构的IC设计中的规范，分析，综合和报告过程。 规范过程访问设计数据库和脚本文件，并允许用户定义扫描配置信息和扫描链规范（例如，设置扫描路径命令）以定义扫描链的部分。 分析读取设计数据库，并基于设计和定义（例如指定的）扫描元素的推断的扫描元素执行扫描链的架构。 在分析期间，设计数据库中的逻辑不会被更改，并且为用户修改/验证生成脚本。 然后，合成通过基于通过分析计划的扫描链改变设计数据库来实现期望的DFT电路。