公开(公告)号：US5786731A

公开(公告)日：1998-07-28

申请号：US623655

申请日：1996-03-29

申请人： James E. Bales

发明人： James E. Bales

IPC分类号： H03F3/30

CPC分类号： H03F3/3066

摘要： A complementary Class AB output stage including a Class AB complementary common emitter quiescently biased by means of current mirrors and a Class AB complementary emitter follower circuit having its emitters connected to the common emitter stage outputs and its collectors connected to the base terminals of the common emitter transistors thus achieving large output swing and large output drive current with very low quiescent current in the common emitter portion of the circuit.

摘要翻译： 一个互补的AB类输出级，包括通过电流镜静态偏置的AB类互补公共发射极和一个AB类互补射极跟随器电路，其发射极连接到共发射极级输出，其集电极连接到公共发射极的基极 因此在电路的公共发射极部分实现大的输出摆幅和大的输出驱动电流，并具有非常低的静态电流。

公开(公告)号：US5394003A

公开(公告)日：1995-02-28

申请号：US64253

申请日：1993-05-20

申请人： James E. Bales ,  Michael J. Hoskins

发明人： James E. Bales ,  Michael J. Hoskins

IPC分类号： G11C8/00 ,  H03H9/02 ,  H01L29/78

CPC分类号： G11C8/005 ,  H03H9/02976

摘要： An acoustic charge transport device comprises a substrate with a layer disposed thereon; a channel disposed within the layer for providing a propagation path for a surface acoustic wave; a contact operably connected and disposed at one end of the channel for injecting an electronic signal into the channel; a transducer disposed at the one end of the channel for generating and propagating the surface acoustic wave through the channel; a plurality of sensing electrodes operably associated with the channel and disposed along the propagation path of the surface acoustic wave for non-destructively sensing the electronic signal; and a plurality of active buffer circuits each having an input operably connected to respective sensing electrode and an output operably connected to an output circuit.

摘要翻译： 声电荷输送装置包括其上设置有层的基板; 设置在所述层内的用于提供表面声波的传播路径的通道; 可操作地连接并设置在通道的一端处的用于将电子信号注入到通道中的触点; 设置在通道的一端的换能器，用于通过通道产生和传播表面声波; 多个感测电极，其可操作地与所述通道相关联并沿着所述表面声波的传播路径设置，用于非破坏性地感测所述电子信号; 以及多个有源缓冲电路，每个有源缓冲器电路各自具有可操作地连接到相应感测电极的输入端和可操作地连接到输出电路的输

公开(公告)号：US5225798A

公开(公告)日：1993-07-06

申请号：US707147

申请日：1991-05-31

申请人： Billy J. Hunsinger ,  James E. Bales

发明人： Billy J. Hunsinger ,  James E. Bales

IPC分类号： H03H15/02

CPC分类号： H03H15/02

摘要： A transversal filter comprises an acoustic charge transport device comprising an input contact for introducing a signal into a buried channel through which the signal is transported by a high frequency acoustic wave and a plurality of non-destructive sense electrodes overlying the channel for successively sampling the signal. A memory device is provided for storing a plurality of tap weight signals, with each tap weight signal for being associated with one of the electrodes. A multiplier system is operably connected with each of the electrodes and with the storage device for generating the product of the signal sampled at each electrode and the associated tap weight signal. A summer is operably associated with the multiplier for summing the products and thereby generating an output signal.

摘要翻译： 横向滤波器包括声电荷传输装置，其包括用于将信号引入掩埋通道的输入触点，通过该掩埋通道，信号由高频声波传输，并且多个非破坏性感测电极覆盖在通道上以连续采样信号 。 提供存储器件用于存储多个抽头加权信号，每个抽头加权信号用于与一个电极相关联。 乘法器系统与每个电极和存储装置可操作地连接，用于产生在每个电极处采样的信号和相关的抽头重量信号的乘积。 夏天可操作地与乘法器相关联以对产物求和，从而产生输出信号。

公开(公告)号：US6114874A

公开(公告)日：2000-09-05

申请号：US75572

申请日：1998-05-11

申请人： James E. Bales

发明人： James E. Bales

IPC分类号： H03K19/0175

CPC分类号： H03K19/017527

摘要： A level translating circuit suitable for converting ECL level signals to CMOS level signals. The ECL signal is converted to a pair of buffered differential signals that are level shifted and divided to produce four transistor drive signal, two of which are connected to the respective gate and source of a P-type MOS transistor and two of which are connected to the respective gate and source of another P-type MOS transistor. An N-type transistor is connected in series with each of the P-type transistors so as to provide CMOS outputs at the junction of the N and P-type transistors.

摘要翻译： 适用于将ECL电平信号转换为CMOS电平信号的电平转换电路。 ECL信号被转换成电平移位和分频的一对缓冲差分信号，以产生四个晶体管驱动信号，其中两个连接到P型MOS晶体管的相应栅极和源极，其中两个连接到 另一个P型MOS晶体管的栅极和源极。 N型晶体管与每个P型晶体管串联连接，以便在N型和P型晶体管的结点处提供CMOS输出。