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公开(公告)号:US08175737B2
公开(公告)日:2012-05-08
申请号:US12374170
申请日:2006-07-19
申请人: Kevin Dean Lucas , Robert Elliott Boone , James Edward Vasek , William Louis Wilkinson , Christophe Couderc
发明人: Kevin Dean Lucas , Robert Elliott Boone , James Edward Vasek , William Louis Wilkinson , Christophe Couderc
摘要: Method and apparatus for designing an integrated circuit by adding a plurality of control points to an integrated circuit wafer design. Each control point has at least one attribute. Then, an integrated circuit wafer is manufactured using the integrated circuit wafer design. A defect on the integrated circuit wafer is then located. The control points are adjusted such that they correspond with the defect.
摘要翻译: 通过向集成电路晶片设计添加多个控制点来设计集成电路的方法和装置。 每个控制点至少有一个属性。 然后,使用集成电路晶片设计制造集成电路晶片。 然后定位集成电路晶片上的缺陷。 调整控制点使其与缺陷相对应。
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公开(公告)号:US20090240364A1
公开(公告)日:2009-09-24
申请号:US12374170
申请日:2006-07-19
申请人: Kevin Dean Lucas , Robert Elliott Boone , James Edward Vasek , William Louis Wilkinson , Christophe Couderc
发明人: Kevin Dean Lucas , Robert Elliott Boone , James Edward Vasek , William Louis Wilkinson , Christophe Couderc
IPC分类号: G06F17/00
摘要: Method and apparatus for designing an integrated circuit by adding a plurality of control points to an integrated circuit wafer design. Each control point has at least one attribute. Then, an integrated circuit wafer is manufactured using the integrated circuit wafer design. A defect on the integrated circuit wafer is then located. The control points are adjusted such that they correspond with the defect.
摘要翻译: 通过向集成电路晶片设计添加多个控制点来设计集成电路的方法和装置。 每个控制点至少有一个属性。 然后,使用集成电路晶片设计制造集成电路晶片。 然后定位集成电路晶片上的缺陷。 调整控制点使其与缺陷相对应。
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