公开(公告)号：US06185722B2

公开(公告)日：2001-02-06

申请号：US09037469

申请日：1998-03-10

申请人： Laura Rohwedder Darden ,  James John Engel ,  Peter Anton Habitz ,  William John Livingstone ,  Daniel Joseph Mainiero ,  Jeannie Harrigan Panner ,  Michael Timothy Trick ,  Paul Steven Zuchowski

发明人： Laura Rohwedder Darden ,  James John Engel ,  Peter Anton Habitz ,  William John Livingstone ,  Daniel Joseph Mainiero ,  Jeannie Harrigan Panner ,  Michael Timothy Trick ,  Paul Steven Zuchowski

IPC分类号： G06F1750

CPC分类号： G06F17/5036 ,  G06F17/5018 ,  G06F2217/36

摘要： A computerized tool or method that calculates the capacitance and resistance of each global wire on the chip, one wire at a time. The invention steps along a track containing a wire segment, grid point by grid point, calculating the resistance and capacitance at that point. At each grid point it searches the neighboring tracks within the surrounding cube for adjacent elements that could cause capacitive effects or affect the resistance of the wire. The method delivers capacitance and resistance values for each process condition for a grid unit length of wire, given the wire type and 3 dimensional environment of the wire segment. The capacitance and resistance at a grid point along the wire are generally determined by one table lookup for wire types based on the surrounding environment. These values are added along wire segments to deliver accurate 3 dimensional capacitances and resistances. The invention can also provide for wires and spaces of various types and widths not provided for in the tables and for calculation of net to net coupling capacitances.

摘要翻译： 一种计算机工具或方法，用于计算芯片上每根全局线的电容和电阻，一次一根线。 本发明沿着包含线段的轨道，通过网格点的网格点，计算该点处的电阻和电容。 在每个网格点，它会搜索相邻元素周围的相邻轨道，以产生电容效应或影响线的电阻。 鉴于线段的线型和三维环境，该方法为网格单元长度的线的每个工艺条件提供电容和电阻值。 沿线的网格点的电容和电阻通常由基于周围环境的电线类型的一个表查找来确定。 这些值沿线段添加以提供精确的3维电容和电阻。 本发明还可以提供在表中未提供的各种类型和宽度的电线和空间以及用于计算网络与网络耦合电容的电线和空间。