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    Three dimensional track-based parasitic extraction
    1.
    发明授权
    Three dimensional track-based parasitic extraction 失效
    基于三维轨道的寄生提取

    公开(公告)号：US06185722B2

    公开(公告)日：2001-02-06

    申请号：US09037469

    申请日：1998-03-10

    申请人： Laura Rohwedder Darden ,  James John Engel ,  Peter Anton Habitz ,  William John Livingstone ,  Daniel Joseph Mainiero ,  Jeannie Harrigan Panner ,  Michael Timothy Trick ,  Paul Steven Zuchowski

    发明人： Laura Rohwedder Darden ,  James John Engel ,  Peter Anton Habitz ,  William John Livingstone ,  Daniel Joseph Mainiero ,  Jeannie Harrigan Panner ,  Michael Timothy Trick ,  Paul Steven Zuchowski

    IPC分类号： G06F1750

    CPC分类号： G06F17/5036 ,  G06F17/5018 ,  G06F2217/36

    摘要： A computerized tool or method that calculates the capacitance and resistance of each global wire on the chip, one wire at a time. The invention steps along a track containing a wire segment, grid point by grid point, calculating the resistance and capacitance at that point. At each grid point it searches the neighboring tracks within the surrounding cube for adjacent elements that could cause capacitive effects or affect the resistance of the wire. The method delivers capacitance and resistance values for each process condition for a grid unit length of wire, given the wire type and 3 dimensional environment of the wire segment. The capacitance and resistance at a grid point along the wire are generally determined by one table lookup for wire types based on the surrounding environment. These values are added along wire segments to deliver accurate 3 dimensional capacitances and resistances. The invention can also provide for wires and spaces of various types and widths not provided for in the tables and for calculation of net to net coupling capacitances.

    摘要翻译： 一种计算机工具或方法，用于计算芯片上每根全局线的电容和电阻，一次一根线。 本发明沿着包含线段的轨道，通过网格点的网格点，计算该点处的电阻和电容。 在每个网格点，它会搜索相邻元素周围的相邻轨道，以产生电容效应或影响线的电阻。 鉴于线段的线型和三维环境，该方法为网格单元长度的线的每个工艺条件提供电容和电阻值。 沿线的网格点的电容和电阻通常由基于周围环境的电线类型的一个表查找来确定。 这些值沿线段添加以提供精确的3维电容和电阻。 本发明还可以提供在表中未提供的各种类型和宽度的电线和空间以及用于计算网络与网络耦合电容的电线和空间。

    Redundant vias
    2.
    发明授权
    Redundant vias 失效
    冗余通孔

    公开(公告)号：US6026224A

    公开(公告)日：2000-02-15

    申请号：US753137

    申请日：1996-11-20

    申请人： Laura Rohwedder Darden ,  William John Livingstone ,  Jeannie Harrigan Panner ,  Patrick Edward Perry ,  William Frank Pokorny ,  Paul Steven Zuchowski

    发明人： Laura Rohwedder Darden ,  William John Livingstone ,  Jeannie Harrigan Panner ,  Patrick Edward Perry ,  William Frank Pokorny ,  Paul Steven Zuchowski

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

    摘要： A wiring design tool which detects minimum area vias and replaces them with redundant vias pairs. The invention uses the definitions for single vias and tracks in a grid coordinate system and a file describing the design wires and their interconnections to select the most favorable direction for the placement. The invention accomplishes this by examining the directions one track away from each single via at various levels and according to the methodology of this invention, detects a possible situs for a redundant via pair, preferably where a segment of wire on the same net already exists. If no design rule violation occurs the system replaces the single via with a redundant via pair.

    摘要翻译： 一种接线设计工具，用于检测最小面积通孔，并用冗余通孔对代替它们。 本发明使用网格坐标系中的单个通孔和轨道的定义以及描述设计线及其互连的文件来选择最有利的放置方向。 本发明通过检查在各个级别上离开每个单个通道一个轨迹的方向来实现这一点，并且根据本发明的方法，检测冗余通路对的可能的位置，优选地，其中已经存在同一网络上的一段电线。 如果没有设计规则违规，系统将使用冗余通路对替换单个通道。