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    Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications
    1.
    发明授权
    Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications 有权
    降低多阈值电压应用中阈值电压容限和偏斜的电路

    公开(公告)号：US07459958B2

    公开(公告)日：2008-12-02

    申请号：US11424961

    申请日：2006-06-19

    申请人： Corey Kenneth Barrows ,  Douglas W. Kemerer ,  Stephen Gerard Shuma ,  Douglas Willard Stout ,  Oscar Conrad Strohacker ,  Mark Steven Styduhar ,  Paul Steven Zuchowski

    发明人： Corey Kenneth Barrows ,  Douglas W. Kemerer ,  Stephen Gerard Shuma ,  Douglas Willard Stout ,  Oscar Conrad Strohacker ,  Mark Steven Styduhar ,  Paul Steven Zuchowski

    IPC分类号： H03K3/01

    CPC分类号： G06F17/5063 ,  H01L27/088 ,  H01L27/092

    摘要： A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit adapted to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit adapted to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator adapted to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

    摘要翻译： 一种用于调整集成电路性能的电路和方法，所述电路包括：具有相应的第一和第二阈值电压的第一和第二组FET，所述第一阈值电压不同于所述第二阈值电压; 包含第一组FET的至少一个FET的第一监视器电路和包含第二组FET的至少一个FET的第二监视电路; 比较电路，其适于基于第一监视电路的性能测量和第二监视电路的性能测量来产生比较信号; 以及控制单元，其适于基于所述比较信号向所述电压调节器产生控制信号，所述电压调节器适于向所述第二组FET的FET的阱提供偏置电压，所述偏置电压的值基于所述控制 信号。

    METHODS AND CIRCUITS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW IN MULTI-THRESHOLD VOLTAGE APPLICATIONS
    2.
    发明申请
    METHODS AND CIRCUITS TO REDUCE THRESHOLD VOLTAGE TOLERANCE AND SKEW IN MULTI-THRESHOLD VOLTAGE APPLICATIONS 审中-公开
    降低多电压电压应用中阈值电压公差和电流的方法和电路

    公开(公告)号：US20080246533A1

    公开(公告)日：2008-10-09

    申请号：US12138514

    申请日：2008-06-13

    申请人： Corey Kenneth Barrows ,  Douglas W. Kemerer ,  Stephen Gerard Shuma ,  Douglas Willard Stout ,  Oscar Conrad Strohacker ,  Mark Steven Styduhar ,  Paul Steven Zuchowski

    发明人： Corey Kenneth Barrows ,  Douglas W. Kemerer ,  Stephen Gerard Shuma ,  Douglas Willard Stout ,  Oscar Conrad Strohacker ,  Mark Steven Styduhar ,  Paul Steven Zuchowski

    IPC分类号： H03K3/01

    CPC分类号： G06F17/5063 ,  H01L27/088 ,  H01L27/092

    摘要： A circuit and a method for adjusting the performance of an integrated circuit, the circuit includes: first and second sets of FETs having respective first and second threshold voltages, the first threshold voltage different from the second threshold voltage; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and a performance measurement of the second monitor circuit; and a control unit configured to generate a control signal to a voltage regulator based on the compare signal, the voltage regulator configured to supply a bias voltage to wells of FETs of the second set of FETs, the value of the bias voltage based on the control signal.

    摘要翻译： 一种用于调整集成电路性能的电路和方法，所述电路包括：具有相应的第一和第二阈值电压的第一和第二组FET，所述第一阈值电压不同于所述第二阈值电压; 包含第一组FET的至少一个FET的第一监视器电路和包含第二组FET的至少一个FET的第二监视电路; 比较电路，被配置为基于所述第一监视电路的性能测量和所述第二监视电路的性能测量来产生比较信号; 以及控制单元，被配置为基于所述比较信号向电压调节器产生控制信号，所述电压调节器被配置为向所述第二组FET的FET的阱提供偏置电压，所述偏置电压的值基于所述控制 信号。

    Three dimensional track-based parasitic extraction
    9.
    发明授权
    Three dimensional track-based parasitic extraction 失效
    基于三维轨道的寄生提取

    公开(公告)号：US06185722B2

    公开(公告)日：2001-02-06

    申请号：US09037469

    申请日：1998-03-10

    申请人： Laura Rohwedder Darden ,  James John Engel ,  Peter Anton Habitz ,  William John Livingstone ,  Daniel Joseph Mainiero ,  Jeannie Harrigan Panner ,  Michael Timothy Trick ,  Paul Steven Zuchowski

    发明人： Laura Rohwedder Darden ,  James John Engel ,  Peter Anton Habitz ,  William John Livingstone ,  Daniel Joseph Mainiero ,  Jeannie Harrigan Panner ,  Michael Timothy Trick ,  Paul Steven Zuchowski

    IPC分类号： G06F1750

    CPC分类号： G06F17/5036 ,  G06F17/5018 ,  G06F2217/36

    摘要： A computerized tool or method that calculates the capacitance and resistance of each global wire on the chip, one wire at a time. The invention steps along a track containing a wire segment, grid point by grid point, calculating the resistance and capacitance at that point. At each grid point it searches the neighboring tracks within the surrounding cube for adjacent elements that could cause capacitive effects or affect the resistance of the wire. The method delivers capacitance and resistance values for each process condition for a grid unit length of wire, given the wire type and 3 dimensional environment of the wire segment. The capacitance and resistance at a grid point along the wire are generally determined by one table lookup for wire types based on the surrounding environment. These values are added along wire segments to deliver accurate 3 dimensional capacitances and resistances. The invention can also provide for wires and spaces of various types and widths not provided for in the tables and for calculation of net to net coupling capacitances.

    摘要翻译： 一种计算机工具或方法，用于计算芯片上每根全局线的电容和电阻，一次一根线。 本发明沿着包含线段的轨道，通过网格点的网格点，计算该点处的电阻和电容。 在每个网格点，它会搜索相邻元素周围的相邻轨道，以产生电容效应或影响线的电阻。 鉴于线段的线型和三维环境，该方法为网格单元长度的线的每个工艺条件提供电容和电阻值。 沿线的网格点的电容和电阻通常由基于周围环境的电线类型的一个表查找来确定。 这些值沿线段添加以提供精确的3维电容和电阻。 本发明还可以提供在表中未提供的各种类型和宽度的电线和空间以及用于计算网络与网络耦合电容的电线和空间。

    Redundant vias
    10.
    发明授权
    Redundant vias 失效
    冗余通孔

    公开(公告)号：US6026224A

    公开(公告)日：2000-02-15

    申请号：US753137

    申请日：1996-11-20

    申请人： Laura Rohwedder Darden ,  William John Livingstone ,  Jeannie Harrigan Panner ,  Patrick Edward Perry ,  William Frank Pokorny ,  Paul Steven Zuchowski

    发明人： Laura Rohwedder Darden ,  William John Livingstone ,  Jeannie Harrigan Panner ,  Patrick Edward Perry ,  William Frank Pokorny ,  Paul Steven Zuchowski

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F2217/12 ,  Y02P90/265

    摘要： A wiring design tool which detects minimum area vias and replaces them with redundant vias pairs. The invention uses the definitions for single vias and tracks in a grid coordinate system and a file describing the design wires and their interconnections to select the most favorable direction for the placement. The invention accomplishes this by examining the directions one track away from each single via at various levels and according to the methodology of this invention, detects a possible situs for a redundant via pair, preferably where a segment of wire on the same net already exists. If no design rule violation occurs the system replaces the single via with a redundant via pair.

    摘要翻译： 一种接线设计工具，用于检测最小面积通孔，并用冗余通孔对代替它们。 本发明使用网格坐标系中的单个通孔和轨道的定义以及描述设计线及其互连的文件来选择最有利的放置方向。 本发明通过检查在各个级别上离开每个单个通道一个轨迹的方向来实现这一点，并且根据本发明的方法，检测冗余通路对的可能的位置，优选地，其中已经存在同一网络上的一段电线。 如果没有设计规则违规，系统将使用冗余通路对替换单个通道。