公开(公告)号：US4633437A

公开(公告)日：1986-12-30

申请号：US624660

申请日：1984-06-26

申请人： David S. Mothersole ,  Lester M. Crudele ,  James L. Tietjen ,  Robert R. Thompson

发明人： David S. Mothersole ,  Lester M. Crudele ,  James L. Tietjen ,  Robert R. Thompson

IPC分类号： G06F9/00 ,  G06F3/00 ,  G06F12/04 ,  G06F13/36 ,  G06F13/38 ,  G06F13/40 ,  G06F15/00

CPC分类号： G06F13/387 ,  G06F13/4018

摘要： In a data processor adapted to perform operations upon operands of a given size, a bus controller is provided to communicate the operands with a storage device having a data port which may be a submultiple of the operand size. In response to a signal from the bus controller requesting the transfer of an operand of a particular size, the storage device provides a size signal indicating the size of the data port available to accommodate the requested transfer. Depending upon the size of the operand to be transferred and the size of the data port of the storage device, the bus controller may break the operand transfer cycle into several bus cycles in order to completely transfer the operand. In the process, the bus controller compensates for any address misalignment between the operand and the data port. In order to distinguish individual operand cycles from the several bus cycles which may comprise the operand cycle, the bus controller provides an operand cycle start signal only at the start of the first bus cycle of each operand cycle.

摘要翻译： 在适于对给定尺寸的操作数执行操作的数据处理器中，提供总线控制器以将操作数与具有可能是操作数大小的数字端口的存储设备通信。 响应于来自总线控制器的请求传送特定大小的操作数的信号，存储设备提供指示可用于容纳所请求传送的数据端口的大小的大小信号。 根据要传输的操作数的大小和存储设备的数据端口的大小，总线控制器可能会将操作数传输周期中断到几个总线周期，以便完全传输操作数。 在此过程中，总线控制器补偿操作数与数据端口之间的任何地址不对齐。 为了区分各个操作数周期与可能包括操作数周期的几个总线周期，总线控制器仅在每个操作数周期的第一个总线周期开始时提供操作数周期开始信号。