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公开(公告)号：US4633437A
公开(公告)日：1986-12-30
申请号：US624660
申请日：1984-06-26
CPC分类号： G06F13/387 , G06F13/4018
摘要： In a data processor adapted to perform operations upon operands of a given size, a bus controller is provided to communicate the operands with a storage device having a data port which may be a submultiple of the operand size. In response to a signal from the bus controller requesting the transfer of an operand of a particular size, the storage device provides a size signal indicating the size of the data port available to accommodate the requested transfer. Depending upon the size of the operand to be transferred and the size of the data port of the storage device, the bus controller may break the operand transfer cycle into several bus cycles in order to completely transfer the operand. In the process, the bus controller compensates for any address misalignment between the operand and the data port. In order to distinguish individual operand cycles from the several bus cycles which may comprise the operand cycle, the bus controller provides an operand cycle start signal only at the start of the first bus cycle of each operand cycle.
摘要翻译： 在适于对给定尺寸的操作数执行操作的数据处理器中，提供总线控制器以将操作数与具有可能是操作数大小的数字端口的存储设备通信。 响应于来自总线控制器的请求传送特定大小的操作数的信号，存储设备提供指示可用于容纳所请求传送的数据端口的大小的大小信号。 根据要传输的操作数的大小和存储设备的数据端口的大小，总线控制器可能会将操作数传输周期中断到几个总线周期，以便完全传输操作数。 在此过程中，总线控制器补偿操作数与数据端口之间的任何地址不对齐。 为了区分各个操作数周期与可能包括操作数周期的几个总线周期，总线控制器仅在每个操作数周期的第一个总线周期开始时提供操作数周期开始信号。
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公开(公告)号：US4744049A
公开(公告)日：1988-05-10
申请号：US97277
申请日：1987-09-17
IPC分类号： G01R31/3185 , G06F11/22 , G06F11/267 , G06F12/00 , G11C29/16 , G06F9/00
CPC分类号： G06F11/2236 , G11C29/16 , G01R31/318516 , G06F11/2273 , G06F12/00
摘要： In a microcoded data processor, an instruction is provided which enables the microaddress for the micromachine to be externally specified. By way of this instruction, the processor may be directed to execute special microcoded routines otherwise unavailable during normal execution. These special microcoded routines may perform useful functions such as testing in an expeditious manner portions of the circuitry of the processor which would otherwise be difficult to test. For example, the functionality of regular structures such as instruction decoding and control programmable logic arrays (PLA's) may either be gated directly out to the tester or internally analyzed before the accumulated results are presented to the tester. On-board instruction caches may also be efficiently exercised to verify that the tag portion properly determines "hits" and "misses", and that the actual instruction cache portion functions accurately.
摘要翻译： 在微编码数据处理器中，提供使外部指定微机器的微地址的指令。 通过该指令，处理器可以被指示执行在正常执行期间不可用的特殊的微编码例程。 这些特殊的微编码例程可以执行有用的功能，例如以快速的方式测试处理器的电路的部分，否则将难以测试。 例如，诸如指令解码和控制可编程逻辑阵列（PLA）的常规结构的功能可以在将累积结果呈现给测试者之前直接门控到测试器或内部分析。 还可以有效地执行车载指令高速缓存以验证标签部分是否适当地确定“命中”和“未命中”，并且实际指令高速缓存部分准确地起作用。
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公开(公告)号：US4698747A
公开(公告)日：1987-10-06
申请号：US750396
申请日：1985-06-28
CPC分类号： G06F15/7832 , G06F9/3867
摘要： An execution unit for a microprocessor comprising a first section for performing arithmetic and logic operations on data, a second section for performing arithmetic operations on data memory addresses, and a third section for performing arithmetic operations on instruction addresses is disclosed in which data addresses and instruction addresses may be simultaneously calculated.
摘要翻译： 一种用于微处理器的执行单元，包括用于对数据执行算术和逻辑运算的第一部分，用于对数据存储器地址执行算术运算的第二部分和用于对指令地址执行算术运算的第三部分，其中数据地址和指令 可以同时计算地址。
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公开(公告)号：US4763253A
公开(公告)日：1988-08-09
申请号：US931029
申请日：1986-11-17
IPC分类号： G06F9/38
CPC分类号： G06F9/3804
摘要： A microcomputer has the capacity for executing instructions, requesting prefetches of instructions, and experiencing a change in instruction flow, or a branch. The microcomputer also knows in advance that a change in instruction flow is going to occur. At such time that a branch becomes known there may also be a pending instruction prefetch request. Because a branch is going to occur, there is no need to execute the prefetch. Consequently, the pending instruction prefetch is flushed which thus avoids wasting time making an unnecessary instruction prefetch.
摘要翻译： 微型计算机具有执行指令的能力，请求预取指令，以及经历指令流程改变或分支。 微型计算机也预先知道将要发生指令流的改变。 在这样一个分支变得已知的时候，也可能有一个挂起的指令预取请求。 因为分支将要发生，所以不需要执行预取。 因此，等待指令预取被刷新，从而避免浪费时间进行不必要的指令预取。
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公开(公告)号：US4751632A
公开(公告)日：1988-06-14
申请号：US861742
申请日：1986-05-07
CPC分类号： G06F13/4018 , G06F13/4234
摘要： In a data processor adapted to perform operations upon operands of a given size, a bus controller is provided to communicate the operands with a storage device having a data port which may be a submultiple of the operand size. In response to a signal from the bus controller requesting the transfer of an operand of a particular size, the storage device provides a size signal indicating the size of the data port available to accommodate the requested transfer. Depending upon the size of the operand to be transferred and the size of the data port of the storage device, the bus controller may break the operand transfer cycle into several bus cycles in order to completely transfer the operand. In the process, the bus controller compensates for any address misalignment between the operand and the data port. In order to distinguish individual operand cycles from the several bus cycles which may comprise the operand cycle, the bus controller provides an operand cycle start signal only at the start of the first bus cycle of each operand cycle.
摘要翻译： 在适于对给定尺寸的操作数执行操作的数据处理器中，提供总线控制器以将操作数与具有可能是操作数大小的数字端口的存储设备通信。 响应于来自总线控制器的请求传送特定大小的操作数的信号，存储设备提供指示可用于容纳所请求传送的数据端口的大小的大小信号。 根据要传输的操作数的大小和存储设备的数据端口的大小，总线控制器可能会将操作数传输周期中断到几个总线周期，以便完全传输操作数。 在此过程中，总线控制器补偿操作数与数据端口之间的任何地址不对齐。 为了区分各个操作数周期与可能包括操作数周期的几个总线周期，总线控制器仅在每个操作数周期的第一个总线周期开始时提供操作数周期开始信号。
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6.发明授权Microcomputer which prioritizes instruction prefetch requests and data operand requests 失效微型计算机，其优先级为指令预取请求和数据操作数请求
公开(公告)号：US4729093A
公开(公告)日：1988-03-01
申请号：US22613
申请日：1987-03-04
CPC分类号： G06F9/3802 , G06F9/3824
摘要： A microcomputer prioritizes data operand requests and instruction prefetch requests. Such prioritizing is established by established criteria. The established priority is altered upon the occurrence of a signal. The signal indicates a certain type of data requests. This data request type is deemed to have a higher priority than is typical for a data request. Consequently, in response to receiving the signal which indicates this data request type, the priority is altered so as to be more inclined to perform the data request. This is particularly useful when performing numerous consecutive data operations, such as a co-processor interface operation.
摘要翻译： 微型计算机对数据操作数请求和指令预取请求进行优先级排序。 这种优先次序是按照既定标准确定的。 确定的优先级在信号发生时被改变。 信号表示某种类型的数据请求。 该数据请求类型被认为具有比典型的数据请求更高的优先级。 因此，响应于接收到指示该数据请求类型的信号，改变优先级以便更倾向于执行数据请求。 这在执行许多连续的数据操作（例如协处理器接口操作）时特别有用。
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公开(公告)号：US4584640A
公开(公告)日：1986-04-22
申请号：US624864
申请日：1984-06-27
CPC分类号： G06F9/30032
摘要： In a data processing system having linked lists it is useful to be able to add and delete items from such lists while maintaining the integrity of the linked nature of such lists. A new compare and swap instruction provides for effectively simultaneously swapping 2 values which is useful for safely adding and deleting items from linked lists. Prior to the instruction the status of the two value are read at the locations to be swapped. During the instruction these locations are checked again to ensure that no change has occurred at these locations before the instruction performs the swap of the two new values. The instruction then performs the proposed 2 value swap but only if no change has occurred at these two locations where the swap is to be performed.
摘要翻译： 在具有链表的数据处理系统中，能够从这些列表中添加和删除项目是有用的，同时保持这种列表的链接性质的完整性。 一个新的比较和交换指令提供有效地同时交换2个值，这对于从链表安全地添加和删除项目是有用的。 在指令之前，在要交换的位置读取两个值的状态。 在指令期间，这些位置再次被检查，以确保在指令执行两个新值的交换之前，这些位置没有发生变化。 然后，该指令执行所提出的2值交换，但只有在要执行交换的两个位置发生任何变化时才执行。
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8.发明授权Microcoded processor executing microroutines with a user specified starting microaddress 失效微编码处理器用户指定启动微地址执行微程序
公开(公告)号：US4887203A
公开(公告)日：1989-12-12
申请号：US165409
申请日：1988-02-26
IPC分类号： G01R31/3185 , G06F9/22 , G06F11/267
CPC分类号： G06F11/2236 , G06F9/226 , G01R31/318516
摘要： In a microcoded data processor, an instruction is provided which enables the microaddress for the micromachine to be externally specified. By way of this instruction, the processor may be directed to execute special microcoded routines otherwise unavailable during normal execution. These special microcoded routines may perform useful functions such as testing in an expeditious manner portions of the circuitry of the processor which would otherwise be difficult to test. For example, the functionality of regular structures such as instruction decoding and control programmable logic arrays (PLA's) may either be gated directly out to the tester or internally analyzed before the accumulated results are presented to the tester. On-board instruction caches may also be efficiently exercised to verify that the tag portion properly determines "hits" and "misses", and that the actual instruction cache portion functions accurately.
摘要翻译： 在微编码数据处理器中，提供使外部指定微机器的微地址的指令。 通过该指令，处理器可以被指示执行在正常执行期间不可用的特殊的微编码例程。 这些特殊的微编码例程可以执行有用的功能，例如以快速的方式测试处理器的电路的部分，否则将难以测试。 例如，诸如指令解码和控制可编程逻辑阵列（PLA）的常规结构的功能可以在将累积结果呈现给测试者之前直接门控到测试器或内部分析。 还可以有效地执行车载指令高速缓存以验证标签部分是否适当地确定“命中”和“未命中”，并且实际指令高速缓存部分准确地起作用。
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9.发明授权Data processor having selective breakpoint capability with minimal overhead 失效具有选择性断点能力的数据处理器具有最小的开销
公开(公告)号：US4635193A
公开(公告)日：1987-01-06
申请号：US867404
申请日：1986-05-13
CPC分类号： G06F11/3648 , G06F9/3005 , G06F9/34
摘要： A data processor communicates with a peripheral device and selectively sets breakpoints with minimal overhead. The data processor utilizes an instruction register to store instructions to be executed. Control means communicate with the peripheral device to selectively set a breakpoint in a software program. When repetitions of the breakpoint are encountered, an exception handler is only executed at the desired breakpoint to minimize overhead. A control portion of the processor selectively receives a breakpoint instruction and stores the breakpoint instruction in the instruction register.
摘要翻译： 数据处理器与外围设备进行通信，并以最小的开销选择性地设置断点。 数据处理器利用指令寄存器来存储要执行的指令。 控制装置与外围设备进行通信，以选择性地设置软件程序中的断点。 当遇到断点的重复时，异常处理程序只在所需的断点处执行，以最小化开销。 处理器的控制部分选择性地接收断点指令并将断点指令存储在指令寄存器中。
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10.发明授权Method and apparatus for coordinating execution of an instruction by a coprocessor 失效用于协调由协处理器执行指令的方法和装置
公开(公告)号：US4729094A
公开(公告)日：1988-03-01
申请号：US30241
申请日：1987-03-24
CPC分类号： G06F9/3861 , G06F9/3881
摘要： A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word. Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives which define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.
摘要翻译： 使用标准总线周期将处理器与协处理器进行接口的系统。 处理器在其指令流中遇到具有特定操作字格式的指令时，将将操作字后的命令字传送到由操作字中的协处理器标识字段指定的特定协处理器。 在解码命令字后，协处理器将响应一组响应原语中的任何一个，这些响应原语定义了协处理器要求处理器在协处理器支持命令时执行的功能。 该接口提供了协处理器可能需要的所有功能，包括向适当的异常处理程序选择性向量化。
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