利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

14 条记录 (耗时 0.015 秒)

    System and method for optimizing phase locked loop damping coefficient
    1.
    发明申请
    System and method for optimizing phase locked loop damping coefficient 审中-公开
    用于优化锁相环阻尼系数的系统和方法

    公开(公告)号：US20060119442A1

    公开(公告)日：2006-06-08

    申请号：US11297511

    申请日：2005-12-08

    申请人： Mir Azam ,  James Lundberg

    发明人： Mir Azam ,  James Lundberg

    IPC分类号： H03L7/00

    摘要： An adjustable oscillator for dynamically optimizing a damping coefficient of a PLL circuit including a gain controlled oscillator circuit and a damping controller. The PLL circuit provides a loop control signal indicative of an error between first and second clock signals and generates a third clock signal which has a frequency which is a clock multiplier times the frequency of the second clock signal. The oscillator circuit has a control input receiving the loop control signal, a gain control input, and an output that provides the third clock signal. The damping controller has an input receiving the clock multiplier and an output providing a gain control signal to the gain control input of the oscillator circuit. The damping controller adjusts gain of the oscillator circuit in response to changes of the clock multiplier to minimize variation of the damping coefficient.

    摘要翻译： 一种用于动态优化包括增益控制振荡器电路和阻尼控制器的PLL电路的阻尼系数的可调谐振荡器。 PLL电路提供指示第一和第二时钟信号之间的误差的回路控制信号，并产生第三时钟信号，该第三时钟信号的频率是时钟乘数乘以第二时钟信号的频率。 振荡器电路具有接收环路控制信号的控制输入，增益控制输入和提供第三时钟信号的输出。 阻尼控制器具有接收时钟倍频器的输入端和向振荡器电路的增益控制输入端提供增益控制信号的输出端。 阻尼控制器响应于时钟乘法器的变化来调节振荡器电路的增益，以最小化阻尼系数的变化。

    Phase locked loop damping coefficient correction mechanism
    2.
    发明申请
    Phase locked loop damping coefficient correction mechanism 审中-公开
    锁相环阻尼系数校正机制

    公开(公告)号：US20060119441A1

    公开(公告)日：2006-06-08

    申请号：US11297510

    申请日：2005-12-08

    申请人： Mir Azam ,  James Lundberg

    发明人： Mir Azam ,  James Lundberg

    IPC分类号： H03L7/00

    CPC分类号： H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/18 ,  H03L2207/04 ,  H03L2207/05

    摘要： A damping coefficient correction mechanism for a PLL circuit including a gain controlled oscillator circuit, a damping controller, and gain compensation logic. The PLL circuit provides a loop control signal indicative of an error between first and second clock signals for generating a third clock signal having a frequency which is a clock multiplier times the frequency of the second clock signal. The oscillator has a control input receiving the loop control signal, a gain control input, and an output that provides the third clock signal. The damping controller has an input receiving the clock multiplier and an output providing a gain control signal to the gain control input of the oscillator. The damping controller adjusts gain of the oscillator in response to changes of the clock multiplier. The gain compensation logic is programmable and adjusts the gain control signal.

    摘要翻译： 一种用于PLL电路的阻尼系数校正机构，包括增益控制振荡电路，阻尼控制器和增益补偿逻辑。 PLL电路提供指示第一和第二时钟信号之间的误差的回路控制信号，用于产生具有时钟乘数乘以第二时钟信号频率的频率的第三时钟信号。 振荡器具有接收环路控制信号的控制输入，增益控制输入和提供第三时钟信号的输出。 阻尼控制器具有接收时钟倍增器的输入端和向振荡器的增益控制输入端提供增益控制信号的输出端。 阻尼控制器根据时钟乘法器的变化调节振荡器的增益。 增益补偿逻辑是可编程的，并调整增益控制信号。

    Damping coefficient variation mechanism in a phase locked loop
    3.
    发明申请
    Damping coefficient variation mechanism in a phase locked loop 审中-公开
    锁相环阻尼系数变化机理

    公开(公告)号：US20060119443A1

    公开(公告)日：2006-06-08

    申请号：US11297622

    申请日：2005-12-08

    申请人： Mir Azam ,  James Lundberg

    发明人： Mir Azam ,  James Lundberg

    IPC分类号： H03L7/00

    CPC分类号： H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03L7/18 ,  H03L2207/04 ,  H03L2207/05

    摘要： A damping coefficient variation mechanism for a PLL including a bias controller, a gain control circuit, and an oscillator circuit. The PLL receives an input clock signal and provides an output clock at a frequency that is the frequency of the input clock multiplied by a clock multiplier. The bias controller has an input receiving a loop control signal and an output providing one or more bias signals. The gain control circuit has bias inputs receiving the bias signals, a gain control input receiving a gain control value, and an output providing a control signal. The oscillator circuit has an input receiving the control signal and an output providing the output clock signal. The gain control circuit provides the control signal to adjust frequency of the output clock signal based on the loop control signal at a gain determined by the gain control value.

    摘要翻译： 一种用于PLL的阻尼系数变化机构，包括偏置控制器，增益控制电路和振荡器电路。 PLL接收输入时钟信号，并以输入时钟频率乘以时钟倍频的频率提供输出时钟。 偏置控制器具有接收回路控制信号的输入端和提供一个或多个偏置信号的输出。 增益控制电路具有接收偏置信号的偏置输入，接收增益控制值的增益控制输入和提供控制信号的输出。 振荡器电路具有接收控制信号的输入端和提供输出时钟信号的输出。 增益控制电路提供控制信号，以由增益控制值确定的增益基于环路控制信号来调节输出时钟信号的频率。

    APPARATUS AND METHOD FOR ENABLING A MULTI-PROCESSOR ENVIRONMENT ON A BUS
    4.
    发明申请
    APPARATUS AND METHOD FOR ENABLING A MULTI-PROCESSOR ENVIRONMENT ON A BUS 有权
    在总线上实现多处理器环境的装置和方法

    公开(公告)号：US20070085560A1

    公开(公告)日：2007-04-19

    申请号：US11422001

    申请日：2006-06-02

    申请人： Darius Gaskins ,  James Lundberg

    发明人： Darius Gaskins ,  James Lundberg

    IPC分类号： H03K19/003

    CPC分类号： G06F13/4086

    摘要： The present invention provides a technique for enabling multiple devices to be interfaced together over a bus that requires dynamic impedance controls. In one embodiment, an apparatus is provided for enabling a multi-device environment on a bus, where the bus requires active termination impedance control. The apparatus includes a first node and multi-processor logic. The first node receives an indication that a corresponding device is at a physical end of the bus. The multi-processor logic is coupled to the first node. The multi-processor logic controls how a second node is driven according to the indication, where the second node is coupled to the bus.

    摘要翻译： 本发明提供了一种使多个设备能够通过需要动态阻抗控制的总线连接在一起的技术。 在一个实施例中，提供了一种用于在总线上实现多设备环境的装置，其中总线需要主动终端阻抗控制。 该装置包括第一节点和多处理器逻辑。 第一节点接收到相应设备处于总线的物理端的指示。 多处理器逻辑耦合到第一节点。 多处理器逻辑控制如何根据第二节点耦合到总线的指示来驱动第二节点。

    N-domino output latch
    5.
    发明申请
    N-domino output latch 有权
    N-domino输出锁存器

    公开(公告)号：US20060033534A1

    公开(公告)日：2006-02-16

    申请号：US11251517

    申请日：2005-10-14

    申请人： James Lundberg ,  Raymond Bertram

    发明人： James Lundberg ,  Raymond Bertram

    IPC分类号： H03K19/096

    CPC分类号： H03K19/0963

    摘要： An N-domino latch includes a domino stage, a write stage, an inverter, a high keeper path, a low keeper path, and an output stage. The domino stage is coupled to an approximately symmetric clock signal. The domino stage evaluates a logic function according to the states of at least one data signal and the approximately symmetric clock signal, where the domino stage pre-charges a pre-charged node high when the approximately symmetric clock signal is low, and discharges the pre-charged node to a low state if the logic function evaluates when the approximately symmetric clock signal is high, and keeps the pre-charged node high if the logic function fails to evaluate when the approximately symmetric clock signal is high, where a latching state of the at least one data signal is provided to the domino stage when the approximately symmetric clock signal is high.

    摘要翻译： N多米诺锁存器包括多米诺骨牌阶段，写阶段，逆变器，高保持者路径，低守护者路径和输出阶段。 多米诺骨牌阶段耦合到近似对称的时钟信号。 多米诺骨牌阶段根据至少一个数据信号和近似对称的时钟信号的状态来评估逻辑功能，其中，当近似对称的时钟信号为低时，多米诺舞台预充电节点为高电平，并且放电预先 如果逻辑功能在大致对称的时钟信号为高时评估逻辑功能，并且如果逻辑功能未能评估何时近似对称的时钟信号为高，则将预充电节点保持为高电平，其中锁定状态 当大致对称的时钟信号为高时，至少一个数据信号被提供给多米诺骨牌阶段。

    P-domino register
    6.
    发明申请
    P-domino register 有权
    多米诺骨牌登记册

    公开(公告)号：US20060038589A1

    公开(公告)日：2006-02-23

    申请号：US11251384

    申请日：2005-10-14

    申请人： James Lundberg ,  Raymond Bertram

    发明人： James Lundberg ,  Raymond Bertram

    IPC分类号： H03K19/096

    CPC分类号： H03K19/0963

    摘要： A P-domino register includes a domino stage, a write stage, an inverter, a low keeper path, a high keeper path, and an output stage. The domino stage is coupled to a pulsed clock signal, and evaluates a logic function according to the states of at least one data signal and the pulsed clock signal, where the domino stage pre-charges a pre-charged node low when the pulsed clock signal is high, and discharges the pre-charged node to a high state if the logic function evaluates when the pulsed clock signal is low, and keeps the pre-charged node low if the logic function fails to evaluate when the pulsed clock signal is low, where a setup state of the at least one data signal is provided to the domino stage when the pulsed clock signal is high.

    摘要翻译： 多米诺骨牌寄存器包括多米诺骨牌阶段，写阶段，逆变器，低保持者路径，高守护者路径和输出阶段。 多米诺舞台与脉冲时钟信号耦合，并根据至少一个数据信号和脉冲时钟信号的状态评估逻辑功能，其中多米诺舞台预充电节点为低电平时，脉冲时钟信号 如果逻辑功能评估脉冲时钟信号为低电平时，将预充电节点放电到高电平状态，并且如果逻辑功能未能评估脉冲时钟信号为低电平时，将预充电节点保持在低电平， 其中当脉冲时钟信号为高时，至少一个数据信号的设置状态被提供给多米诺骨牌阶段。

    P-domino output latch with accelerated evaluate path
    8.
    发明申请
    P-domino output latch with accelerated evaluate path 有权
    P-domino输出锁存器加速评估路径

    公开(公告)号：US20050248368A1

    公开(公告)日：2005-11-10

    申请号：US10834900

    申请日：2004-04-28

    申请人： Raymond Bertram ,  James Lundberg

    发明人： Raymond Bertram ,  James Lundberg

    IPC分类号： H03K19/096

    CPC分类号： H03K19/0963

    摘要： An apparatus and method are provided for accelerating the evaluated output of an P-domino latch. The apparatus includes evaluation P-logic, latching logic, keeper logic, and acceleration logic. The evaluation P-logic is coupled to a first N-channel device at a pre-charged node, and is configured to evaluate a logic function based on at least one input data signal. The latching logic is coupled and responsive to a clock signal and the pre-charged node. The latching logic controls the state of a latch node based on the state of the pre-charged node during an evaluation period between a first edge of said clock signal and a second edge of the clock signal. The latching logic otherwise presents a tri-state condition to the latch node. The keeper logic is coupled to the latch node. The keeper logic maintains the state of the latch node when the tri-state condition is presented, and provides a complementary state of the latch node at a complementary latch node. The acceleration logic is coupled and responsive to the pre-charged node and the complementary latch node, and is configured to control the state of an output node.

    摘要翻译： 提供了一种用于加速P-domino闩锁的评估输出的装置和方法。 该装置包括评估P逻辑，锁存逻辑，保持器逻辑和加速度逻辑。 评估P逻辑在预充电节点处耦合到第一N沟道器件，并且被配置为基于至少一个输入数据信号来评估逻辑功能。 锁存逻辑被耦合并响应于时钟信号和预充电节点。 所述锁存逻辑在所述时钟信号的第一边缘和所述时钟信号的第二边沿之间的评估周期期间基于所述预充电节点的状态来控制锁存节点的状态。 闭锁逻辑否则向锁存节点呈现三态条件。 保持器逻辑耦合到锁存节点。 当呈现三态条件时，保持器逻辑维持锁存节点的状态，并且在互补锁存节点处提供锁存节点的互补状态。 加速度逻辑被耦合并响应于预充电节点和互补锁存节点，并且被配置为控制输出节点的状态。

    Dynamic logic register
    9.
    发明申请
    Dynamic logic register 有权
    动态逻辑寄存器

    公开(公告)号：US20050046446A1

    公开(公告)日：2005-03-03

    申请号：US10925307

    申请日：2004-08-24

    申请人： Imran Qureshi ,  James Lundberg

    发明人： Imran Qureshi ,  James Lundberg

    IPC分类号： G11C19/00 ,  G11C19/28 ,  H03K19/096

    CPC分类号： G11C19/28 ,  G11C19/00

    摘要： A dynamic logic register including a complementary pair of evaluation devices, delayed inversion logic, a dynamic evaluator, latching logic, and a keeper circuit coupled to the output. The evaluation devices are responsive to a clock signal and provide a pre-charged node and an evaluation node. The delayed inversion logic outputs a complete signal that is a delayed and inverted version of the clock signal. The dynamic evaluator, coupled between the pre-charged and evaluation nodes, evaluates a logic function based on a data signal during an evaluation period between operative edges of the clock and complete signals. The latching logic enables the state of an output node to be determined by the state of the pre-charged node during the evaluation period and otherwise clamps the pre-charged node to prevent perturbations of the data signal from propagating to the output node.

    摘要翻译： 一种动态逻辑寄存器，包括一对互补的评估装置，延迟反转逻辑，动态评估器，锁存逻辑以及耦合到输出的保持器电路。 评估装置响应于时钟信号并提供预充电节点和评估节点。 延迟反相逻辑输出作为时钟信号的延迟和反相版本的完整信号。 耦合在预充电节点和评估节点之间的动态评估器在时钟的工作边缘和完成信号之间的评估周期期间基于数据信号评估逻辑功能。 锁存逻辑使得输出节点的状态能够在评估期间由预充电节点的状态确定，否则将预充电节点钳位以防止数据信号的扰动传播到输出节点。