公开(公告)号：US5559972A

公开(公告)日：1996-09-24

申请号：US981930

申请日：1992-11-24

申请人： Maurice E. Carey ,  Gerald H. Miracle ,  James T. Moyer ,  Richard A. Neuner

发明人： Maurice E. Carey ,  Gerald H. Miracle ,  James T. Moyer ,  Richard A. Neuner

IPC分类号： G06F13/12 ,  G06F13/14 ,  G06F13/42

CPC分类号： G06F13/122

摘要： In a data processing system in which an extender unit interconnects the parallel bus of a control unit and a serial link of an extender channel, the channel and the extender unit send and receive serial frames that permit the extender unit to operate under the protocol of the parallel bus with either byte mode devices or non-byte mode devices. The control unit can be modified to operate with a byte mode device in data streaming, a high speed data transfer mode.

摘要翻译： 在其中扩展器单元将控制单元的并行总线和扩展器信道的串行链路互连的数据处理系统中，信道和扩展器单元发送和接收允许扩展器单元在协议的协议下操作的串行帧 并行总线与任一字节模式器件或非字节模式器件。 在数据流，高速数据传输模式中，可以修改控制单元以使用字节模式设备进行操作。

公开(公告)号：US5003465A

公开(公告)日：1991-03-26

申请号：US212292

申请日：1988-06-27

申请人： Douglas R. Chisholm ,  Robert G. Iseminger ,  Richard A. Kelley ,  Wan L. Leung ,  James T. Moyer ,  Mark C. Snedaker

发明人： Douglas R. Chisholm ,  Robert G. Iseminger ,  Richard A. Kelley ,  Wan L. Leung ,  James T. Moyer ,  Mark C. Snedaker

IPC分类号： G06F13/36 ,  G06F13/28

CPC分类号： G06F13/28

摘要： In a computer system, a plurality of input/output processors (IOP's) are connected via an asynchronous input/output bus, called an "SPD" bus, to one side of an input/output interface controller (IOIC). The other side of the IOIC is connected to a storage controller (SC) via a synchronous bus called an "adapter" bus. The SC is connected to a common system memory and possibly also to an instruction processing unit. The IOIC comprises at least one shared DMA facility for executing DMA read/write storage operations requested by the IOP's via the SPD bus. Each shared DMA facility includes a buffer for holding control information and data to be transmitted between the SC and one of the IOP's. This enables the SPD bus to be released for utilization by otehr IOP's connected thereto during periods of "storage latency" that occur after a DMA storage operation has been initiated by one IOP.

公开(公告)号：US4580265A

公开(公告)日：1986-04-01

申请号：US509699

申请日：1983-06-30

申请人： David N. Gooding ,  Stefan P. Jackowski ,  James T. Moyer ,  James W. Plant, III

发明人： David N. Gooding ,  Stefan P. Jackowski ,  James T. Moyer ,  James W. Plant, III

IPC分类号： H04L1/00 ,  G06F11/10

CPC分类号： G06F11/10

摘要： A failure detection apparatus detects the existence of an abnormal circuit condition in a circuit which causes a subsequently transmitted data byte to be transmitted from one integrated circuit to another integrated circuit out of sequence relative to a previously transmitted data byte. Even and odd data bytes are received by the first integrated circuit with odd parity. However, the even data byte is transmitted from the first integrated circuit to the second integrated circuit, along existing interface lines extending between the integrated circuits, with odd parity. The parity bit of the odd data byte is inverted, the odd data byte being transmitted along the existing interface lines with even parity. An exclusive OR gate in the second integrated circuit receives the parity bit of the even data byte and passes the parity bit without inversion in response to a first state of a clock signal from an odd latch; however, the exclusive OR gate, upon receipt of the odd data byte, re-inverts the parity bit of the odd data byte in response to a second state of the clock signal. A parity checker compares the data bits of the incoming even and odd data bytes with the parity bit generated by the exclusive OR gate and generates an error check signal representative of the receipt of the subsequently transmitted data byte transmitted out of sequence relative to the previously transmitted data byte when the combined parity of the data bits and parity bit at the input of the parity checker is not odd.

摘要翻译： 故障检测装置检测电路中是否存在异常电路状况，该电路使随后发送的数据字节相对于先前发送的数据字节从一个集成电路发送到另一个集成电路。 偶数和奇数数据字节由具有奇校验的第一集成电路接收。 然而，偶数数据字节从具有奇数奇偶校验的集成电路之间沿现有接口线传输从第一集成电路传输到第二集成电路。 奇数数据字节的奇偶校验位反转，奇数数据字节沿现有的接口线以偶校验发送。 第二集成电路中的异或门接收偶数数据字节的奇偶校验位，并响应于来自奇数锁存器的时钟信号的第一状态而不反转地通过奇偶校验位; 然而，异或门在接收到奇数数据字节时响应于时钟信号的第二状态重新反转奇数数据字节的奇偶校验位。 奇偶校验器将输入偶数和奇数数据字节的数据位与异或门产生的奇偶校验位进行比较，并产生一个错误检查信号，代表随后发送的数据字节的接收，该序列相对于先前传输 当奇偶检验器的输入端的数据位和奇偶校验位的组合奇偶校验不是奇数时的数据字节。

公开(公告)号：US4561094A

公开(公告)日：1985-12-24

申请号：US508772

申请日：1983-06-29

申请人： Stefan P. Jackowski ,  James T. Moyer

发明人： Stefan P. Jackowski ,  James T. Moyer

IPC分类号： G06F13/00 ,  G06F11/00 ,  G06F11/16 ,  G06F13/36

CPC分类号： G06F11/0751 ,  G06F11/1625

摘要： Interface lines interconnect a first circuit to a second circuit. When an abnormal circuit condition affects the interface lines, such as an open circuit or a short circuit condition, the operation of the first and second circuit is detrimentally affected. This invention determines the existence of abnormal circuit conditions in one or more lines of a group of interface lines without using redundant duplex lines. The interface lines are subdivided into a first group, which are used when the apparatus of the present invention is being used to locate abnormal circuit conditions, and a second group, which are not used when the apparatus of the present invention is being used to locate abnormal circuit conditions. Each line of the first group is connected, at its input side, to a corresponding input terminal of a first exclusive-or gate and, at its output side, to a corresponding input terminal of a second exclusive-or gate. The first and second exclusive-or gates are input to a matching circuit, an output signal from the matching circuit indicating the existence of an abnormal circuit condition in the first group of lines. One line of the first group is connected to an input side of the second group. The output side of the second group is connected to an additional input terminal of the second exclusive-or gate. An output signal from the matching circuit indicates the existence of an abnormal circuit condition in at least one line of either one or both of the first and second group of lines.

摘要翻译： 接口线将第一电路互连到第二电路。 当异常电路状况影响接口线路（例如开路或短路状况）时，第一和第二电路的操作受到不利影响。 本发明在不使用冗余双工线路的情况下确定一组接口线路中的一条或多条线路中存在异常电路状况。 接口线分为第一组，当本发明的装置用于定位异常电路条件时使用的第一组，以及当本发明的装置用于定位时不使用的第二组 异常电路条件。 第一组的每一行在其输入侧连接到第一异或门的相应输入端，并且在其输出侧连接到第二异或门的相应输入端。 第一和第二异或门被输入到匹配电路，来自匹配电路的输出信号指示第一组线路中存在异常电路状况。 第一组的一行连接到第二组的输入侧。 第二组的输出侧连接到第二异或门的附加输入端。 来自匹配电路的输出信号表示在第一组和第二组中的任何一个或两个的至少一行中存在异常电路状况。

公开(公告)号：US4131940A

公开(公告)日：1978-12-26

申请号：US818797

申请日：1977-07-25

申请人： James T. Moyer

发明人： James T. Moyer

IPC分类号： G06F3/06 ,  G06F5/06 ,  G06F12/08 ,  G06F13/12 ,  G06F13/00 ,  G06F3/00

CPC分类号： G06F13/122

摘要： Channel data buffer apparatus for buffering data being transferred between an input/output channel unit and a main storage unit in a digital data processing system. In the disclosed embodiment, data is generally transferred between the channel unit and the data buffer (a "channel/buffer" transfer) in two-byte segments and between the main storage unit and the data buffer (a "storage/buffer" transfer) in eight-byte segments. The data buffer is comprised of eight column-forming byte-wide multirow storage arrays each having its own address mechanism for accessing any desired row therein. Corresponding rows in the different storage arrays provide the corresponding eight-byte rows for the data buffer as a whole. For storage/buffer transfers, data buffer address circuitry is provided for enabling a group of eight contiguous bytes to be read out of or written into the data buffer on a single access even though some of the bytes may be located on one row of the data buffer and other of the bytes on the next row of the data buffer. For channel/buffer transfers, data buffer address circuitry is provided for enabling a group of two contiguous bytes to be read out of or written into the data buffer on a single access even though one of the bytes may be located on one row of the data buffer and the other of the bytes on the next row of the data buffer. For storage/buffer transfers, an eight-byte wrap-around data shifter is located between the data buffer and the main storage unit for enabling any necessary alignment or realignment of the data being transferred. These features enable data to be loaded into the data buffer in a packed manner and without regard to the storage word boundary alignments in the main storage unit. Among other things, this minimizes the hardware needed for buffering the data and improves the data chaining capability of the system.

摘要翻译： 用于在数字数据处理系统中缓冲在输入/输出通道单元和主存储单元之间传输的数据的通道数据缓冲装置。 在所公开的实施例中，数据通常在两字节段之间以及主存储单元和数据缓冲器之间（“存储/缓冲”传送）在信道单元和数据缓冲器之间（“通道/缓冲器”传送） 在八字节段。 数据缓冲器由八个列形成的字节宽的多行存储阵列组成，每个存储阵列具有用于访问其中任何所需行的其自己的地址机制。 不同存储阵列中的相应行为整个数据缓冲区提供了相应的八字节行。 对于存储/缓冲器传送，提供了数据缓冲器地址电路，用于使一组八个连续字节能够在单个访问上读出或写入数据缓冲器，即使某些字节可能位于数据的一行上 缓冲区和数据缓冲区下一行的其他字节。 对于通道/缓冲器传送，提供了数据缓冲器地址电路，用于使一组两个连续字节能够在单个访问上读出或写入数据缓冲器，即使其中一个字节可能位于数据的一行上 缓冲区和数据缓冲区下一行的其他字节。 对于存储/缓冲传输，在数据缓冲器和主存储单元之间设置一个八字节环绕数据移位器，用于启动正在传输的数据的任何必要的对准或重新对准。 这些特征使得能够以压缩的方式将数据加载到数据缓冲器中，而不考虑主存储单元中的存储字边界对准。 除此之外，这最大限度地减少了缓冲数据所需的硬件，并提​​高了系统的数据链接能力。

公开(公告)号：US5097410A

公开(公告)日：1992-03-17

申请号：US292399

申请日：1988-12-30

申请人： Richard L. Hester ,  Stefan P. Jackowski ,  Peter N. James ,  James T. Moyer ,  Robert G. Rush ,  Gregory S. Ulsh ,  Mark J. Wolski

发明人： Richard L. Hester ,  Stefan P. Jackowski ,  Peter N. James ,  James T. Moyer ,  Robert G. Rush ,  Gregory S. Ulsh ,  Mark J. Wolski

IPC分类号： G06F13/12

CPC分类号： G06F13/122

摘要： A system structured to transfer control information between an IFA (I/O interface adapter) and an I/O processor, and I/O data between an IFA and a CDB (channel data buffer) has separate interfaces for these transfers. The control interface includes a multi-mode, bidirectional control data bus, a control mode bus for establishing the mode of the bus, and a check interface on which the IFA provides error information. The data interface includes a multi-mode, bidirectional data transfer bus, respective SYNC and ACCEPT lines for transferring time-phased control signals to establish the mode of the data transfer bus, and a parity line to indicate to the IFA the parity of the SYNC and ACCEPT lines.