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公开(公告)号：US4580265A
公开(公告)日：1986-04-01
申请号：US509699
申请日：1983-06-30
CPC分类号： G06F11/10
摘要： A failure detection apparatus detects the existence of an abnormal circuit condition in a circuit which causes a subsequently transmitted data byte to be transmitted from one integrated circuit to another integrated circuit out of sequence relative to a previously transmitted data byte. Even and odd data bytes are received by the first integrated circuit with odd parity. However, the even data byte is transmitted from the first integrated circuit to the second integrated circuit, along existing interface lines extending between the integrated circuits, with odd parity. The parity bit of the odd data byte is inverted, the odd data byte being transmitted along the existing interface lines with even parity. An exclusive OR gate in the second integrated circuit receives the parity bit of the even data byte and passes the parity bit without inversion in response to a first state of a clock signal from an odd latch; however, the exclusive OR gate, upon receipt of the odd data byte, re-inverts the parity bit of the odd data byte in response to a second state of the clock signal. A parity checker compares the data bits of the incoming even and odd data bytes with the parity bit generated by the exclusive OR gate and generates an error check signal representative of the receipt of the subsequently transmitted data byte transmitted out of sequence relative to the previously transmitted data byte when the combined parity of the data bits and parity bit at the input of the parity checker is not odd.
摘要翻译： 故障检测装置检测电路中是否存在异常电路状况，该电路使随后发送的数据字节相对于先前发送的数据字节从一个集成电路发送到另一个集成电路。 偶数和奇数数据字节由具有奇校验的第一集成电路接收。 然而，偶数数据字节从具有奇数奇偶校验的集成电路之间沿现有接口线传输从第一集成电路传输到第二集成电路。 奇数数据字节的奇偶校验位反转，奇数数据字节沿现有的接口线以偶校验发送。 第二集成电路中的异或门接收偶数数据字节的奇偶校验位，并响应于来自奇数锁存器的时钟信号的第一状态而不反转地通过奇偶校验位; 然而，异或门在接收到奇数数据字节时响应于时钟信号的第二状态重新反转奇数数据字节的奇偶校验位。 奇偶校验器将输入偶数和奇数数据字节的数据位与异或门产生的奇偶校验位进行比较，并产生一个错误检查信号，代表随后发送的数据字节的接收，该序列相对于先前传输 当奇偶检验器的输入端的数据位和奇偶校验位的组合奇偶校验不是奇数时的数据字节。
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2.发明授权Multimode data system for transferring control and data information in an I/O subsystem 失效用于传输I / O子系统中的控制和数据信息的多模数据系统
公开(公告)号：US5097410A
公开(公告)日：1992-03-17
申请号：US292399
申请日：1988-12-30
申请人： Richard L. Hester , Stefan P. Jackowski , Peter N. James , James T. Moyer , Robert G. Rush , Gregory S. Ulsh , Mark J. Wolski
发明人： Richard L. Hester , Stefan P. Jackowski , Peter N. James , James T. Moyer , Robert G. Rush , Gregory S. Ulsh , Mark J. Wolski
IPC分类号： G06F13/12
CPC分类号： G06F13/122
摘要： A system structured to transfer control information between an IFA (I/O interface adapter) and an I/O processor, and I/O data between an IFA and a CDB (channel data buffer) has separate interfaces for these transfers. The control interface includes a multi-mode, bidirectional control data bus, a control mode bus for establishing the mode of the bus, and a check interface on which the IFA provides error information. The data interface includes a multi-mode, bidirectional data transfer bus, respective SYNC and ACCEPT lines for transferring time-phased control signals to establish the mode of the data transfer bus, and a parity line to indicate to the IFA the parity of the SYNC and ACCEPT lines.
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公开(公告)号：US4561094A
公开(公告)日：1985-12-24
申请号：US508772
申请日：1983-06-29
CPC分类号： G06F11/0751 , G06F11/1625
摘要： Interface lines interconnect a first circuit to a second circuit. When an abnormal circuit condition affects the interface lines, such as an open circuit or a short circuit condition, the operation of the first and second circuit is detrimentally affected. This invention determines the existence of abnormal circuit conditions in one or more lines of a group of interface lines without using redundant duplex lines. The interface lines are subdivided into a first group, which are used when the apparatus of the present invention is being used to locate abnormal circuit conditions, and a second group, which are not used when the apparatus of the present invention is being used to locate abnormal circuit conditions. Each line of the first group is connected, at its input side, to a corresponding input terminal of a first exclusive-or gate and, at its output side, to a corresponding input terminal of a second exclusive-or gate. The first and second exclusive-or gates are input to a matching circuit, an output signal from the matching circuit indicating the existence of an abnormal circuit condition in the first group of lines. One line of the first group is connected to an input side of the second group. The output side of the second group is connected to an additional input terminal of the second exclusive-or gate. An output signal from the matching circuit indicates the existence of an abnormal circuit condition in at least one line of either one or both of the first and second group of lines.
摘要翻译： 接口线将第一电路互连到第二电路。 当异常电路状况影响接口线路（例如开路或短路状况）时，第一和第二电路的操作受到不利影响。 本发明在不使用冗余双工线路的情况下确定一组接口线路中的一条或多条线路中存在异常电路状况。 接口线分为第一组，当本发明的装置用于定位异常电路条件时使用的第一组，以及当本发明的装置用于定位时不使用的第二组 异常电路条件。 第一组的每一行在其输入侧连接到第一异或门的相应输入端，并且在其输出侧连接到第二异或门的相应输入端。 第一和第二异或门被输入到匹配电路，来自匹配电路的输出信号指示第一组线路中存在异常电路状况。 第一组的一行连接到第二组的输入侧。 第二组的输出侧连接到第二异或门的附加输入端。 来自匹配电路的输出信号表示在第一组和第二组中的任何一个或两个的至少一行中存在异常电路状况。
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4.发明授权Shared access control device for integrated system with multiple functional units accessing external structures over multiple data buses 失效用于具有多个功能单元的集成系统的共享访问控制设备通过多个数据总线访问外部结构
公开(公告)号：US6038630A
公开(公告)日：2000-03-14
申请号：US47139
申请日：1998-03-24
CPC分类号： G06F13/4022 , G06F13/1684
摘要： A multi-path access control device for an integrated system is presented which allows simultaneous access to multiple external devices coupled thereto by multiple functional units. The multiple functional units are coupled to the shared access control device across two or more high speed, shared data buses. The control device includes multiple bus ports, each coupled to a different data bus, and a non-blocking crossbar switch coupled to the bus ports for controlling forwarding, with zero cycle latency, of requests from the functional units. Multiple external device ports are coupled to the non-blocking crossbar switch for receiving requests forwarded by the crossbar switch, and each external device is coupled to a different external device port. The crossbar switch allows multiple requests at the bus ports directed to different external devices to be forwarded to different external device ports for simultaneous accessing of different external devices coupled thereto pursuant to the multiple requests.
摘要翻译： 提出了一种用于集成系统的多路径访问控制装置，其允许通过多个功能单元同时访问与其耦合的多个外部设备。 多个功能单元通过两个或更多个高速共享数据总线耦合到共享访问控制设备。 控制设备包括多个总线端口，每个总线端口耦合到不同的数据总线，以及耦合到总线端口的非阻塞交叉开关，用于控制来自功能单元的请求的零周期等待时间的转发。 多个外部设备端口耦合到非阻塞交叉开关，用于接收由交叉开关转发的请求，并且每个外部设备耦合到不同的外部设备端口。 交叉开关允许在指向不同外部设备的总线端口上的多个请求被转发到不同的外部设备端口，以便根据多个请求同时访问与其耦合的不同外部设备。
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公开(公告)号：US5539895A
公开(公告)日：1996-07-23
申请号：US241910
申请日：1994-05-12
申请人： James W. Bishop , Charles E. Carmack, Jr. , Patrick W. Gallagher , Stefan P. Jackowski , Gregory R. Klouda , Robert D. Siegl
发明人： James W. Bishop , Charles E. Carmack, Jr. , Patrick W. Gallagher , Stefan P. Jackowski , Gregory R. Klouda , Robert D. Siegl
CPC分类号： G06F12/08 , G06F12/0811 , G06F12/0808
摘要： A hierarchical cache system comprises a plurality of first level cache subsystems for storing data or instructions of respective CPUs, a higher level cache subsystem containing data or instructions of the plurality of cache subsystems, and a main memory coupled to the higher level cache subsystem. A page mover is coupled to the higher level cache subsystem and main memory, and responds to a request from one of the CPUs to store data into the main memory, by storing the data into the main memory without copying previous contents of a store-to address of the request to the higher level cache subsystem in response to said request. Also, the page mover invalidates the previous contents in the higher level cache subsystem if already resident there when the CPU made the request. A buffering system within the page mover comprises request buffers and data segment buffers to store a segment of predetermined size of the data. When all of the request buffers have like priority and there are fewer request buffers that contain respective, outstanding requests than the number of data segment buffers, the page mover means allocates to the request buffers with outstanding requests use of the data segment buffers for which there are no outstanding requests.
摘要翻译： 分级缓存系统包括用于存储相应CPU的数据或指令的多个第一级高速缓存子系统，包含多个高速缓存子系统的数据或指令的更高级高速缓存子系统以及耦合到较高级缓存子系统的主存储器。 页面移动器耦合到较高级缓存子系统和主存储器，并且通过将数据存储到主存储器中来响应来自一个CPU的请求以将数据存储到主存储器中，而不复制存储器的先前内容 响应于所述请求向高级缓存子系统发送请求的地址。 而且，当CPU发出请求时，页面移动器使上级缓存子系统中的先前内容无效。 页面移动器中的缓冲系统包括请求缓冲器和数据段缓冲器，以存储数据的预定大小的段。 当所有请求缓冲器都具有优先级，并且存在比数据段缓冲器数量多的请求缓冲器，该请求缓冲器包含与数据段缓冲器数目相对应的未完成请求时，页移动器装置向未请求的请求缓冲器分配请求使用数据段缓冲器 没有未完成的请求。
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公开(公告)号：US06968415B2
公开(公告)日：2005-11-22
申请号：US10113299
申请日：2002-03-29
CPC分类号： G06F13/4059
摘要： An opaque memory region for a bridge of an I/O adapter. The opaque memory region is inaccessible to memory transactions which traverse the bridge either from a primary bus to secondary bus or secondary bus to primary bus. As a result, memory transactions which target the opaque memory region are ignored by the bridge, allowing for the same address to exist on both sides of the bridge with different data stored in each. The implementation of the opaque memory region provides a means to complete memory transactions within I/O adapter subsystem memory, hence, relieving host computer system memory resources. In addition, a number of I/O adapters can be used in a host computer system where the host and all the I/O devices use some of the same memory addresses.
摘要翻译： 用于I / O适配器的桥的不透明的存储器区域。 不透明的存储器区域无法通过从主总线到次总线或辅助总线到主总线的桥接器的存储器事务。 因此，桥接器忽略了针对不透明存储器区域的内存事务，允许在每个存储不同数据的网桥两侧存在相同的地址。 不透明存储器区域的实现提供了在I / O适配器子系统存储器内完成存储器事务的手段，因此减轻了主机计算机系统存储器资源。 此外，主机和所有I / O设备使用一些相同的内存地址的主机系统中可以使用多个I / O适配器。
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公开(公告)号：US4809273A
公开(公告)日：1989-02-28
申请号：US8505
申请日：1987-01-29
IPC分类号： G06F11/10 , G06F11/267 , H03M13/00 , G06F11/12
CPC分类号： G06F11/2215 , G06F11/10
摘要： A system for ensuring accurate transmission of data between two functional units. A checking code generator is provided and a device operatively connected to the checking code generator ensures proper operation thereof.
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公开(公告)号：US20100132048A1
公开(公告)日：2010-05-27
申请号：US12323670
申请日：2008-11-26
IPC分类号： G06F21/00
CPC分类号： G06F21/554 , G06F21/78 , G06F21/81 , G06F2221/2143
摘要： A circuit arrangement, method, and design structure for controlling access to master secret data disposed in at least a portion of at least one persistent region of an integrated circuit device is disclosed. The circuit arrangement includes a clock circuit responsive to an external clock signal, a security state machine configured to control a security state of the integrated circuit device, and a master secret circuit in communication with the security state machine and configured to control access to the master secret data. The security state machine and master secret circuit are isolated from the clock circuit, and the master secret circuit is responsive to the security state machine to selectively erase at least a portion of the master secret data. The master secret circuit may be configured to erase the portion of the master secret data in response to a null or triggered security state.
摘要翻译： 公开了一种用于控制对设置在集成电路装置的至少一个持续区域的至少一部分中的主秘密数据的访问的电路装置，方法和设计结构。 电路装置包括响应于外部时钟信号的时钟电路，被配置为控制集成电路装置的安全状态的安全状态机以及与安全状态机通信并被配置为控制对主机的访问的主秘密电路 秘密资料。 安全状态机和主秘密电路与时钟电路隔离，并且主秘密电路响应于安全状态机来选择性地擦除主秘密数据的至少一部分。 主秘密电路可以被配置为响应于空或触发的安全状态来擦除主秘密数据的部分。
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9.发明授权System for controlling multiple port/multiple channel I/O configuration according to communication request initiation status 失效根据通信请求启动状态控制多端口/多通道I / O配置的系统
公开(公告)号：US5418909A
公开(公告)日：1995-05-23
申请号：US226221
申请日：1994-04-11
CPC分类号： G06F13/126
摘要： The I/O configuration of a computer system includes two channels which are capable of being available on up to four interface ports, with the ports being incorporated within the channel in order to eliminate the need for an external switch. Control indicators are provided for monitoring the communications request initiation status of each channel and each port to achieve expeditious transfers through a selected port between the channel and peripheral devices. The I/O configuration is established responsive to the communications request initiation status that indicates one of several states depending on which side initiates a request and whether the connection has been made.
摘要翻译： 计算机系统的I / O配置包括能够在多达四个接口端口上可用的两个信道，其中端口被并入信道内，以便不需要外部交换机。 提供控制指示器，用于监视每个通道和每个端口的通信请求启动状态，以实现通道和外围设备之间选定端口的快速传输。 响应于通信请求发起状态建立I / O配置，该状态指示根据哪个方启动请求以及是否建立了连接的几种状态之一。
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公开(公告)号：US10452844B2
公开(公告)日：2019-10-22
申请号：US12323670
申请日：2008-11-26
摘要： A circuit arrangement, method, and design structure for controlling access to master secret data disposed in at least a portion of at least one persistent region of an integrated circuit device is disclosed. The circuit arrangement includes a clock circuit responsive to an external clock signal, a security state machine configured to control a security state of the integrated circuit device, and a master secret circuit in communication with the security state machine and configured to control access to the master secret data. The security state machine and master secret circuit are isolated from the clock circuit, and the master secret circuit is responsive to the security state machine to selectively erase at least a portion of the master secret data. The master secret circuit may be configured to erase the portion of the master secret data in response to a null or triggered security state.
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