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    Method of timing model abstraction for circuits containing simultaneously switching internal signals
    1.
    发明申请
    Method of timing model abstraction for circuits containing simultaneously switching internal signals 失效
    包含同时切换内部信号的电路的定时模型抽象方法

    公开(公告)号：US20060031797A1

    公开(公告)日：2006-02-09

    申请号：US10897349

    申请日：2004-07-22

    Applicant: Jeffrey Soreff ,  James Warnock

    Inventor： Jeffrey Soreff ,  James Warnock

    IPC: G06F17/50

    CPC classification number: G06F17/5031

    Abstract: The present invention provides for determining arrival times in a circuit. An arrival time for a main signal is assigned. An arrival time for a secondary signal is assigned. It is determined whether a test is for an early arrival or for a later arrival. If the test type is for a late arrival, it is determined whether the arrival time for the secondary signal is later than for the first signal. If the test type is for an early arrival, it is determined whether the arrival time for the secondary signal is earlier than for the first signal. If the test type is for the late arrival and the arrival time for the secondary signal is later than for the first signal, assuming maximum interference between the signals. If the test type is for the late arrival and the arrival time for the secondary signal is not later than for the first signal, calculating the actual interference between the signals.

    Abstract translation: 本发明提供了确定电路中的到达时间。 分配主信号的到达时间。 分配辅助信号的到达时间。 确定测试是提前到达还是稍后到达。 如果测试类型是迟到的，则确定辅助信号的到达时间是否晚于第一信号。 如果测试类型是用于提前到达，则确定辅助信号的到达时间是否早于第一信号。 如果测试类型是迟到的，并且辅助信号的到达时间晚于第一信号，则假定信号之间的最大干扰。 如果测试类型为迟到，并且次要信号的到达时间不晚于第一信号，则计算信号之间的实际干扰。

    Method and system for controlling a complementary user interface on a display surface
    3.
    发明授权
    Method and system for controlling a complementary user interface on a display surface 失效
    用于控制显示表面上的补充用户界面的方法和系统

    公开(公告)号：US07340682B2

    公开(公告)日：2008-03-04

    申请号：US10435397

    申请日：2003-05-09

    Applicant: D. David Nason ,  J. Scott Campbell ,  Phillip Brooks ,  Carson Kaan ,  Thomas C. O'Rourke ,  James Warnock ,  John Easton

    Inventor： D. David Nason ,  J. Scott Campbell ,  Phillip Brooks ,  Carson Kaan ,  Thomas C. O'Rourke ,  James Warnock ,  John Easton

    IPC: G06F3/00

    CPC classification number: G09G5/14 ,  G06F9/451 ,  G09G1/16 ,  G09G1/165 ,  G09G2310/0232 ,  G09G2370/027

    Abstract: An alternate display content controller provides a technique for controlling a video display separately from and in addition to the content displayed on the operating system display surface. Where the display is a computer monitor, the alternate display content controller interacts with the computer utility operating system and hardware drivers to control allocation of display space and create and control one or more parallel graphical user interfaces adjacent the operating system desktop. An alternate display content controller may be incorporated in either hardware or software. As software, an alternate display content controller may be an application running on the computer operating system, or may include an operating system kernel of varying complexity ranging from dependent on the utility operating system for hardware system services to a parallel system independent of the utility operating system and capable of supporting dedicated applications. The alternate display content controller may also include content and operating software delivered over the internet or any other LAN. The alternate display content controller may also be included in a television decoder/settop box to permit two or more parallel graphical user interfaces to be displayed simultaneously.

    Abstract translation: 替代的显示内容控制器提供用于与显示在操作系统显示表面上的内容分离地以及除了显示在操作系统显示表面上的内容之外控制视频显示的技术 在显示器是计算机监视器的情况下，备用显示内容控制器与计算机实用程序操作系统和硬件驱动程序交互以控制显示空间的分配，并创建和控制与操作系统桌面相邻的一个或多个并行图形用户界面。 备用显示内容控制器可以并入硬件或软件中。 作为软件，备用显示内容控制器可以是在计算机操作系统上运行的应用，或者可以包括不同复杂度的操作系统内核，从依赖于用于硬件系统服务的公用事业操作系统到独立于公用事业操作的并行系统 系统并能够支持专用应用。 备用显示内容控制器还可以包括通过互联网或任何其他LAN传递的内容和操作软件。 备用显示内容控制器也可以包括在电视解码器/机顶盒中以允许同时显示两个或更多个并行图形用户界面。

    Scan Chain Disable Function for Power Saving
    4.
    发明申请
    Scan Chain Disable Function for Power Saving 失效
    扫描链禁用功能用于省电

    公开(公告)号：US20070061647A1

    公开(公告)日：2007-03-15

    申请号：US11552807

    申请日：2006-10-25

    Applicant: Sang Dhong ,  Joel Silberman ,  Osamu Takahashi ,  James Warnock ,  Dieter Wendel

    Inventor： Sang Dhong ,  Joel Silberman ,  Osamu Takahashi ,  James Warnock ,  Dieter Wendel

    IPC: G01R31/28

    CPC classification number: G06F1/3203 ,  G06F1/325

    Abstract: An apparatus, a method and a computer program product are provided for conserving energy during functional mode of a processor by disabling the scan chain. By inserting logic gating into the scan chain it is possible to disable the scan chain during the processor's functional mode. During functional mode the scan out port of the latch bit in a scan chain toggles, which leads to unnecessary energy consumption. By gating scan control signals and the scan out port of a latch bit, the scan chain segment between latch bits can be disconnected. Therefore, the scan control signals can disable the scan chain during functional mode.

    Abstract translation: 提供了一种装置，方法和计算机程序产品，用于通过禁用扫描链来在处理器的功能模式期间节省能量。 通过将逻辑门控插入到扫描链中，可以在处理器的功能模式期间禁用扫描链。 在功能模式期间，扫描链中锁存位的扫描输出端口切换，这导致不必要的能量消耗。 通过门控扫描控制信号和锁存位的扫描输出端口，可以断开锁存位之间的扫描链段。 因此，扫描控制信号可以在功能模式下禁用扫描链。

    Methods for modeling latch transparency
    5.
    发明申请
    Methods for modeling latch transparency 有权
    锁定透明度建模方法

    公开(公告)号：US20050071794A1

    公开(公告)日：2005-03-31

    申请号：US10962121

    申请日：2004-10-08

    Applicant: Erwin Behnen ,  Jeffrey Soreff ,  James Warnock ,  Dieter Wendel

    Inventor： Erwin Behnen ,  Jeffrey Soreff ,  James Warnock ,  Dieter Wendel

    IPC: G06F9/45 ,  G06F17/50

    CPC classification number: G06F17/5022

    Abstract: In a first aspect, a method is provided that includes the steps of (1) receiving a circuit design having a plurality of latches; and (2) allowing one or more latches of the circuit design to be locally treated as exhibiting latch transparency during modeling of the timing behavior of the circuit design. Numerous other aspects are provided.

    Abstract translation: 在第一方面中，提供了一种方法，包括以下步骤：（1）接收具有多个锁存器的电路设计; 以及（2）允许电路设计的一个或多个闩锁在电路设计的定时行为建模期间被局部处理为呈现闩锁透明度。 提供了许多其他方面。

    Regular local clock buffer placement and latch clustering by iterative optimization
    7.
    发明授权
    Regular local clock buffer placement and latch clustering by iterative optimization 有权
    通过迭代优化进行常规本地时钟缓冲放置和锁存器聚类

    公开(公告)号：US08104014B2

    公开(公告)日：2012-01-24

    申请号：US12022951

    申请日：2008-01-30

    Applicant: Ruchir Puri ,  Haifeng Qian ,  Chin Ngai Sze ,  James Warnock

    Inventor： Ruchir Puri ,  Haifeng Qian ,  Chin Ngai Sze ,  James Warnock

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F2217/62

    Abstract: Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance of the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally design a clock network by logically assigning clusters of the latches to respective clock distribution structures, placing clock pins at favored pin locations, and placing clock distribution structures directly underneath the clock pins. The clock distribution structures may be moved to favored distribution locations along the clock stripes, and new optimal clustering generated between the latches and the clock distribution structures. These three optimizations are preferably repeated iteratively to derive a local optimal solution for the clock network.

    Abstract translation: 电源，路由和电迁移已成为现代微处理器设计中的关键问题。 在高性能设计中，时钟是功耗最大的消费者。 安排时钟组件的规律性，以便最小化时钟网络的电容可以帮助减少时钟功率，但是，由于物理放置这些组件的一些灵活性，可能会损害性能。 本发明提供了通过将锁存器的簇逻辑地分配到相应的时钟分布结构来优化设计时钟网络的技术，将时钟引脚置于有利的引脚位置，并将时钟分配结构直接放置在时钟引脚下方。 时钟分配结构可以沿着时钟条移动到有利的分配位置，并且在锁存器和时钟分配结构之间产生新的最优聚类。 优选地重复地重复这三个优化以导出时钟网络的局部最优解。

    REGULAR LOCAL CLOCK BUFFER PLACEMENT AND LATCH CLUSTERING BY ITERATIVE OPTIMIZATION
    9.
    发明申请
    REGULAR LOCAL CLOCK BUFFER PLACEMENT AND LATCH CLUSTERING BY ITERATIVE OPTIMIZATION 有权
    通过迭代优化的常规本地时钟缓冲器放置和锁存器

    公开(公告)号：US20090193377A1

    公开(公告)日：2009-07-30

    申请号：US12022951

    申请日：2008-01-30

    Applicant: Ruchir Puri ,  Haifeng Qian ,  Chin Ngai Sze ,  James Warnock

    Inventor： Ruchir Puri ,  Haifeng Qian ,  Chin Ngai Sze ,  James Warnock

    IPC: G06F17/50

    CPC classification number: G06F17/5077 ,  G06F2217/62

    Abstract: Power, routability and electromigration have become crucial issues in modem microprocessor designs. In high performance designs, clocks are the highest consumer of power. Arranging clocking components with regularity so as to minimize the capacitance of the clock nets can help reduce clock power, however, it may hurt performance due to some loss of flexibility in physically placing those components. The present invention provides techniques to optimally design a clock network by logically assigning clusters of the latches to respective clock distribution structures, placing clock pins at favored pin locations, and placing clock distribution structures directly underneath the clock pins. The clock distribution structures may be moved to favored distribution locations along the clock stripes, and new optimal clustering generated between the latches and the clock distribution structures. These three optimizations are preferably repeated iteratively to derive a local optimal solution for the clock network.

    Abstract translation: 电源，路由和电迁移已成为现代微处理器设计中的关键问题。 在高性能设计中，时钟是功耗最大的消费者。 安排时钟组件的规律性，以便最小化时钟网络的电容可以帮助减少时钟功率，但是，由于物理放置这些组件的一些灵活性，可能会损害性能。 本发明提供了通过将锁存器的簇逻辑地分配到相应的时钟分配结构来优化设计时钟网络的技术，将时钟引脚置于有利的引脚位置，并将时钟分配结构直接放置在时钟引脚下方。 时钟分配结构可以沿着时钟条移动到有利的分配位置，并且在锁存器和时钟分配结构之间产生新的最优聚类。 优选地重复地重复这三个优化以导出时钟网络的局部最优解。

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