公开(公告)号：US08817536B2

公开(公告)日：2014-08-26

申请号：US12006228

申请日：2007-12-31

Applicant: Andreas Scade ,  David Still ,  James Allen ,  Jay Ashokkumar ,  Jaskarn Singh Johal

Inventor： Andreas Scade ,  David Still ,  James Allen ,  Jay Ashokkumar ,  Jaskarn Singh Johal

IPC: G11C14/00 ,  G11C11/00

CPC classification number: G11C14/00 ,  G11C14/0063

Abstract: A memory circuit includes a controlled current source coupled to an input to a nonvolatile cell, and a second controlled current source coupled to a volatile cell, the volatile cell coupled to receive current from the controlled current source via the nonvolatile cell.

Abstract translation: 存储器电路包括耦合到非易失性单元的输入的受控电流源和耦合到易失性单元的第二受控电流源，所述易失性单元被耦合以经由非易失性单元从受控电流源接收电流。

公开(公告)号：US08467243B1

公开(公告)日：2013-06-18

申请号：US12888737

申请日：2010-09-23

Applicant: Kaveh Shakeri ,  Jay Ashokkumar

Inventor： Kaveh Shakeri ,  Jay Ashokkumar

IPC: G11C11/34

CPC classification number: G11C11/4125 ,  G11C14/0081

Abstract: A process of operating a memory circuit involves RECALLing a state of a volatile memory cell from a nonvolatile memory cell, and inverting an output of the volatile memory cell after every other RECALL.

Abstract translation: 操作存储器电路的过程涉及从非易失性存储单元回收易失性存储器单元的状态，并且在每隔一个RECALL之后反转易失性存储器单元的输出。

公开(公告)号：US20080232167A1

公开(公告)日：2008-09-25

申请号：US12006228

申请日：2007-12-31

Applicant: Andreas Scade ,  David Still ,  James Allen ,  Jay Ashokkumar ,  Johal Jas

Inventor： Andreas Scade ,  David Still ,  James Allen ,  Jay Ashokkumar ,  Johal Jas

IPC: G11C7/00 ,  G11C14/00

CPC classification number: G11C14/00 ,  G11C14/0063

Abstract: A memory circuit includes a controlled current source coupled to an input to a nonvolatile cell, and a second controlled current source coupled to a volatile cell, the volatile cell coupled to receive current from the controlled current source via the nonvolatile cell.

Abstract translation: 存储器电路包括耦合到非易失性单元的输入的受控电流源和耦合到易失性单元的第二受控电流源，所述易失性单元被耦合以经由非易失性单元从受控电流源接收电流。