公开(公告)号：US07865857B1

公开(公告)日：2011-01-04

申请号：US11657659

申请日：2007-01-23

申请人： Amit Chopra ,  Ian Gebbie ,  Donald O'Riordan ,  Sumit Arora ,  Jean-Daniel Sonnard

发明人： Amit Chopra ,  Ian Gebbie ,  Donald O'Riordan ,  Sumit Arora ,  Jean-Daniel Sonnard

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F17/5068

摘要： Features are provided for graphically representing constraints on design objects in an Electronic Design Automation tool. A particular constraint on one or more circuit objects is displayed as a highlighted region that extends to each visible circuit object to which the constraint applies. Attributes of the highlighted region, such as density and thickness, may proportionally represent attributes of the constraint, such as a strength or distance specified by the constraint. The highlighted region is superimposed on or around circuit objects. The highlighted region may be a halo, which is a partially transparent region filled with a color. Multiple regions that represent the same type of constraint or relationship are connected by line segments, providing the ability to visualize groups of constrained objects, including groups that span levels of a hierarchical design. Intersecting highlighted regions are blended together using techniques such as alpha blending.

摘要翻译： 提供了在电子设计自动化工具中图形化表示设计对象约束的特性。 对一个或多个电路对象的特定约束被显示为突出显示的区域，其延伸到约束所适用的每个可见电路对象。 突出显示区域的属性（如密度和厚度）可以成比例地表示约束的属性，例如由约束指定的强度或距离。 突出显示的区域叠加在电路对象上或周围。 突出显示的区域可以是光晕，其是填充有颜色的部分透明区域。 表示相同类型的约束或关系的多个区域通过线段连接，提供了可视化约束对象组的能力，包括跨层次设计层次的组。 使用诸如α混合的技术将相交突出显示的区域混合在一起。

公开(公告)号：US07418683B1

公开(公告)日：2008-08-26

申请号：US11233809

申请日：2005-09-21

申请人： Jean-Daniel Sonnard ,  Zhigang Wang ,  Hemanth Sampath

发明人： Jean-Daniel Sonnard ,  Zhigang Wang ,  Hemanth Sampath

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/74

摘要： A computer aided design tool and method for designing IC layouts by recommending subcircuit layout constraints based upon an automated identification from a circuit schematic of subcircuit types requiring special IC layout constraints. Subcircuit types are identified on the basis of netlist examination, as well as cues from the layout of the circuit schematic.

摘要翻译： 一种用于设计IC布局的计算机辅助设计工具和方法，其通过基于需要特殊IC布局约束的子电路类型的电路原理图的自动识别来推荐子电路布局约束。 基于网表检查的子电路类型，以及电路原理图布局的线索。