Branch prediction unit for high-performance processor
    1.
    发明授权
    Branch prediction unit for high-performance processor 失效
    用于高性能处理器的分支预测单元

    公开(公告)号:US5394529A

    公开(公告)日:1995-02-28

    申请号:US86355

    申请日:1993-07-01

    IPC分类号: F02B75/02 G06F9/38 G06F9/26

    CPC分类号: G06F9/3848 F02B2075/025

    摘要: A pipelined CPU executes instructions of variable length, and references memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A branch prediction method employs a branch history table which records the taken vs. not-taken history of branch opcodes recently used, and uses an empirical aglorithm to predict which way the next occurrence of this branch will go, based upon the history table. The branch history table stores in each entry a number of bits for each branch address, each bits indicating "taken" or "not-taken" for one occurrence of the branch. The table is indexed by branch address. A register stores the empirical aglorithm, and upon occurrence of a branch its history is fetched from the table and used to select a location in the register containing a prediction for this particular pattern of branch history.

    摘要翻译: 流水线CPU执行可变长度的指令,并使用各种数据宽度引用存储器。 使用宏指令流水线(而不是微指令流水线),在CPU的单元之间排队,以允许指令执行时间的灵活性。 分支预测方法采用分支历史表,其记录最近使用的分支操作码的拍摄历史和未拍摄的历史,并且使用经验法则来基于历史表来预测该分支的下一次出现将如何去除。 分支历史表在每个条目中存储每个分支地址的位数,对于一次分支,每个比特指示“采取”或“未采用”。 表由分支地址索引。 寄存器存储经验法则,并且在出现分支时,其历史从表中取出并用于选择寄存器中的位置,该位置包含该特定分支历史模式的预测。