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1.发明申请SYSTEM AND METHOD TO OPTIMIZE SEMICONDUCTOR POWER BY INTEGRATION OF PHYSICAL DESIGN TIMING AND PRODUCT PERFORMANCE MEASUREMENTS 有权通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法公开(公告)号：US20090217221A1
公开(公告)日：2009-08-27
申请号：US12038320
申请日：2008-02-27
申请人： Theodoros E. ANEMIKOS , Jeanne P. Spence Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
发明人： Theodoros E. ANEMIKOS , Jeanne P. Spence Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G01R31/3008
摘要： A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power.
摘要翻译： 提供了通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法。 该方法包括：建立定时运行并识别用于定时运行的西格玛码; 建立环形振荡器箱和相应的代码; 识别用于第二级组件以满足所选择的电压仓的所需时间运行; 使用所需的时间运行定时产品; 使用定时测试产品的环形振荡器以获得物理设计识别; 记录物理设计识别和时间运行的西格玛码; 并使用记录的物理设计标识和西格玛码来为产品设置电压以优化功率。
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2.发明授权System and method to optimize semiconductor power by integration of physical design timing and product performance measurements 有权通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法公开(公告)号：US07877714B2
公开(公告)日：2011-01-25
申请号：US12038320
申请日：2008-02-27
申请人： Theodoros E. Anemikos , Jeanne P. Spence Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
发明人： Theodoros E. Anemikos , Jeanne P. Spence Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G01R31/3008
摘要： A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power.
摘要翻译： 提供了通过整合物理设计时序和产品性能测量来优化半导体功率的系统和方法。 该方法包括：建立定时运行并识别用于定时运行的西格玛码; 建立环形振荡器箱和相应的代码; 识别用于第二级组件以满足所选择的电压仓的所需时间运行; 使用所需的时间运行定时产品; 使用定时测试产品的环形振荡器以获得物理设计识别; 记录物理设计识别和时间运行的西格玛码; 并使用记录的物理设计标识和西格玛码来为产品设置电压以优化功率。
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3.发明申请METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CUT POINT 失效通过调节选择性电压激活切割点来优化功率的方法公开(公告)号：US20090228843A1
公开(公告)日：2009-09-10
申请号：US12041729
申请日：2008-03-04
申请人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
发明人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circuit devices after manufacture into relatively slow integrated circuits and relatively fast integrated circuit devices. The method selects an initial operating speed cut point to minimize a maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices. The method then manufactures the integrated circuit devices using the integrated circuit design and tests the operating speeds and power consumption levels of the integrated circuit devices. Then, the method adjusts the initial cut point to a final cut point based on the testing, to minimize the maximum power level of the relatively slow integrated circuits and relatively fast integrated circuit devices.
摘要翻译： 在集成电路设计中优化功率使用的方法分析了预期由集成电路设计产生的多个操作速度切割点。 操作速度切割点用于将制造后的相同设计的集成电路器件分成相对较慢的集成电路和相对较快的集成电路器件。 该方法选择初始操作速度切割点以使相对较慢的集成电路和相对快速的集成电路器件的最大功率电平最小化。 然后，该方法使用集成电路设计制造集成电路器件，并测试集成电路器件的工作速度和功耗水平。 然后，该方法基于测试将初始切割点调整到最终切割点，以使相对较慢的集成电路和相对较快的集成电路器件的最大功率电平最小化。
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4.发明授权Method of optimizing power usage of an integrated circuit design by tuning selective voltage binning cut point 失效通过调整选择性电压分档切割点来优化集成电路设计的功耗的方法公开(公告)号：US07810054B2
公开(公告)日：2010-10-05
申请号：US12041729
申请日：2008-03-04
申请人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
发明人： Theodoros E. Anemikos , Jeanne Bickford , Laura S. Chadwick , Susan K. Lichtensteiger , Anthony D. Polson
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method of optimizing power usage in an integrated circuit design analyzes multiple operating speed cut points that are expected to be produced by the integrated circuit design. The operating speed cut points are used to divide identically designed integrated circuit devices after manufacture into relatively slow integrated circuit devices and relatively fast integrated circuit devices. The method selects an initial operating speed cut point to minimize a maximum power consumption level of the relatively slow integrated circuit devices and the relatively fast identically designed integrated circuit devices. The method then manufactures the integrated circuit devices using the integrated circuit design and tests operating speeds and power consumption levels of the identically designed integrated circuit devices. Then, the method adjusts the initial operating speed cut point to a final operating speed cut point based on the testing, to minimize the maximum power consumption level of the relatively slow integrated circuit devices and the relatively fast integrated circuit devices.
摘要翻译： 在集成电路设计中优化功率使用的方法分析了预期由集成电路设计产生的多个操作速度切割点。 操作速度切割点用于将制造后的相同设计的集成电路器件分成相对较慢的集成电路器件和相对较快的集成电路器件。 该方法选择初始操作速度切换点以使相对较慢的集成电路器件和相对快速的相同设计的集成电路器件的最大功耗水平最小化。 该方法然后使用集成电路设计制造集成电路器件，并测试相同设计的集成电路器件的工作速度和功耗水平。 然后，该方法基于测试将初始操作速度切换点调整到最终操作速度切割点，以使相对较慢的集成电路器件和相对快速的集成电路器件的最大功耗水平最小化。
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5.发明授权Method of laying out integrated circuit design based on known polysilicon perimeter densities of individual cells 有权基于单个电池的已知多晶硅周边密度布置集成电路设计的方法公开(公告)号：US07890906B2
公开(公告)日：2011-02-15
申请号：US12117761
申请日：2008-05-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.
摘要翻译： 公开了至少部分地基于这些单元的已知多晶硅周边密度来布置集成电路设计的单个单元的方法。 也就是说，方法实施例使用已知单元的多晶硅周密度的知识来驱动这些单元在芯片上的放置（即，驱动楼层规划）。 方法实施例可以用于实现大致均匀的跨芯片多晶硅周边密度，并且由此限制可归因于多晶硅周边密度变化的功能器件之间的性能参数变化。 或者，方法实施例可以用于选择性地控制芯片的不同区域的平均多晶硅周长密度的变化，从而选择性地控制位于那些不同区域中的功能设备之间的某些性能参数变化。
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6.发明授权Integrated circuit with uniform polysilicon perimeter density, method and design structure 有权具有均匀多晶硅周密度的集成电路，方法和设计结构公开(公告)号：US07849433B2
公开(公告)日：2010-12-07
申请号：US12117771
申请日：2008-05-09
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , G06F17/5072
摘要： Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit.
摘要翻译： 公开了形成具有期望的去耦电容并具有均匀和目标的跨芯片多晶硅周长密度的集成电路的实施例。 该方法包括根据设计布置功能块以形成电路，并且还布置一个或多个去耦电容器块以实现期望的去耦电容。 然后，确定块的局部多晶硅周边密度，并且根据需要重新配置去耦电容器块，以便调整局部多晶硅周边密度的差异。 这种重新配置以基本维持期望的去耦电容的方式执行。 由于跨芯片多晶硅周边密度均匀性，芯片的不同区域中的功能器件将表现出有限的性能参数变化（例如，限制阈值电压变化）。 本文还公开了根据方法实施例形成的集成电路结构和集成电路的设计结构的实施例。
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7.发明授权IC chip design modeling using perimeter density to electrical characteristic correlation 失效IC芯片设计建模使用周边密度与电气特性相关公开(公告)号：US07805693B2
公开(公告)日：2010-09-28
申请号：US12031734
申请日：2008-02-15
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： IC chip design modeling using perimeter density to an electrical characteristic correlation is disclosed. In one embodiment, a method may include determining a perimeter density of conductive structure within each region of a plurality of regions of an integrated circuit (IC) chip design; correlating a measured electrical characteristic within a respective region of an IC chip that is based on the IC chip design to the perimeter density; and modeling the IC chip design based on the correlation.
摘要翻译： 公开了使用周界密度到电特性相关性的IC芯片设计建模。 在一个实施例中，一种方法可以包括确定集成电路（IC）芯片设计的多个区域的每个区域内的导电结构的周边密度; 将基于IC芯片设计的IC芯片的相应区域中的测量电特性与周围密度相关联; 并根据相关性对IC芯片设计进行建模。
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8.发明申请INTEGRATED CIRCUIT WITH UNIFORM POLYSILICON PERIMETER DENSITY, METHOD AND DESIGN STRUCTURE 有权具有均匀多晶硅密度的集成电路，方法和设计结构公开(公告)号：US20090278222A1
公开(公告)日：2009-11-12
申请号：US12117771
申请日：2008-05-09
CPC分类号： H01L27/0207 , G06F17/5072
摘要： Disclosed are embodiments of forming an integrated circuit with a desired decoupling capacitance and with the uniform and targeted across-chip polysilicon perimeter density. The method includes laying out functional blocks to form the circuit according to the design and also laying out one or more decoupling capacitor blocks to achieve the desired decoupling capacitance. Then, local polysilicon perimeter densities of the blocks are determined and, as necessary, the decoupling capacitor blocks are reconfigured in order to adjust for differences in the local polysilicon perimeter densities. This reconfiguring is performed in a manner that essentially maintains the desired decoupling capacitance. Due to the across-chip polysilicon perimeter density uniformity, functional devices in different regions of the chip will exhibit limited performance parameter variations (e.g., limited threshold voltage variations). Also disclosed herein are embodiments of an integrated circuit structure formed according to the method embodiments and a design structure for the integrated circuit.
摘要翻译： 公开了形成具有期望的去耦电容并具有均匀和目标的跨芯片多晶硅周长密度的集成电路的实施例。 该方法包括根据设计布置功能块以形成电路，并且还布置一个或多个去耦电容器块以实现期望的去耦电容。 然后，确定块的局部多晶硅周边密度，并且根据需要重新配置去耦电容器块，以便调整局部多晶硅周边密度的差异。 这种重新配置以基本维持期望的去耦电容的方式执行。 由于跨芯片多晶硅周边密度均匀性，芯片的不同区域中的功能器件将表现出有限的性能参数变化（例如，限制阈值电压变化）。 本文还公开了根据方法实施例形成的集成电路结构和集成电路的设计结构的实施例。
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9.发明申请公开(公告)号：US20090282380A1
公开(公告)日：2009-11-12
申请号：US12117761
申请日：2008-05-09
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Disclosed is a method of laying out individual cells of an integrated circuit design, based at least in part on the known polysilicon perimeter densities of those cells. That is, the method embodiments use the knowledge of polysilicon perimeter density for known cells to drive placement of those cells on a chip (i.e., to drive floor-planning). The method embodiments can be used to achieve approximately uniform across-chip polysilicon perimeter density and, thereby to limit performance parameter variations between functional devices that are attributable to variations in polysilicon perimeter density. Alternatively, the method embodiments can be used to selectively control variations in the average polysilicon perimeter density of different regions of a chip and, thereby to selectively control certain performance parameter variations between functional devices located in those different regions.
摘要翻译： 公开了至少部分地基于这些单元的已知多晶硅周边密度来布置集成电路设计的单个单元的方法。 也就是说，方法实施例使用已知单元的多晶硅周密度的知识来驱动这些单元在芯片上的放置（即，驱动楼层规划）。 方法实施例可以用于实现大致均匀的跨芯片多晶硅周边密度，并且由此限制可归因于多晶硅周边密度变化的功能器件之间的性能参数变化。 或者，方法实施例可以用于选择性地控制芯片的不同区域的平均多晶硅周长密度的变化，从而选择性地控制位于那些不同区域中的功能设备之间的某些性能参数变化。
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10.发明申请IC CHIP DESIGN MODELING USING PERIMETER DENSITY TO ELECTRICAL CHARACTERISTIC CORRELATION 失效使用周密密度进行电子特性关联的IC芯片设计建模公开(公告)号：US20090210834A1
公开(公告)日：2009-08-20
申请号：US12031734
申请日：2008-02-15
IPC分类号： G06F9/45
CPC分类号： G06F17/5081
摘要： IC chip design modeling using perimeter density to an electrical characteristic correlation is disclosed. In one embodiment, a method may include determining a perimeter density of conductive structure within each region of a plurality of regions of an integrated circuit (IC) chip design; correlating a measured electrical characteristic within a respective region of an IC chip that is based on the IC chip design to the perimeter density; and modeling the IC chip design based on the correlation.
摘要翻译： 公开了使用周界密度到电特性相关性的IC芯片设计建模。 在一个实施例中，一种方法可以包括确定集成电路（IC）芯片设计的多个区域的每个区域内的导电结构的周边密度; 将基于IC芯片设计的IC芯片的相应区域中的测量电特性与周围密度相关联; 并根据相关性对IC芯片设计进行建模。
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